Tung Anh Pham - Academia.edu (original) (raw)
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Indian Institute of Science Education and Resarch(IISER), Vithura, Trivandrum, Kerala
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Papers by Tung Anh Pham
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006
As technology evolves, there is a never ending need to explore design tradeoffs and alternatives.... more As technology evolves, there is a never ending need to explore design tradeoffs and alternatives. In the CMOS technologies of the recent past where minimizing the die area was crucial, radix-4 minimally redundant SRT dividers were widely used because they only require simple multiples of divisor. Quotient conversion was typically done by on-the-fly conversion. In deep submicron CMOS technology these decisions need to be reconsidered. Now it is attractive to use maximum redundancy to simplify quotient selection. Replacing the on-the-fly conversion that operates on every cycle with an adder that operates only one cycle reduces the switching factor by the order of 29x for the conversion during a double precision division. This is significant because the onthe-fly conversion can consume 30% of the total energy of a divider. Furthermore, the quotient computation is sped up by the elimination of the big lookup table of minimally redundant SRT dividers. To illustrate this concept of trading extra hardware for improved power and speed and a simpler implementation, a radix-4 maximally redundant divider is designed and implemented in 65 nm CMOS technology using an ASIC flow and single, double and triple V T devices. Clock and data gating and data recirculation techniques are used to save power. Finally, a method to evaluate design alternatives for energy efficiency is proposed that takes into account the active power consumption, the inactive power consumption and the duty cycle.
2006 IEEE International Symposium on Signal Processing and Information Technology, 2006
This paper presents a proposal for design of radix 4 SRT dividers for single precision DSP in dee... more This paper presents a proposal for design of radix 4 SRT dividers for single precision DSP in deep submicron CMOS technology. Radix 4 dividers with minimal redundancy were used widely in the previous technologies where minimizing the die area was the top priority. This was done because these dividers only require simple multiples of divisor, and quotient conversion was typically done by on-the-fly conversion without the need for an adder. On the other hand, in the current deep submicron CMOS technology where many millions of transistors are available in a relatively small silicon area, it is attractive to use an adder and maximum redundancy to simplify quotient selection and conversion. Replacing the on-the-fly conversion that operates on every cycle by an adder that operates only one cycle reduces the switching factor by the order of 6x. This is significant because the on-the-fly conversion can consume 30% of the total energy of a divider. Furthermore, thanks to the elimination of the big lookup table intrinsic in minimally redundant SRT dividers, the quotient computation is sped up. To illustrate this concept of trading a little extra hardware for reduced power and increased speed in the deep submicron CMOS technology, a number of single precision radix 4 dividers with maximal redundancy are designed and implemented in 65 nm CMOS technology using an ASIC flow and triple VT devices. Clock and data gating and data recirculating techniques are used to save power. High VT devices are introduced to reduce leakage power. Finally, a novel method to evaluate different alternatives for energy efficiency is described along with the implementation results.
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006
As technology evolves, there is a never ending need to explore design tradeoffs and alternatives.... more As technology evolves, there is a never ending need to explore design tradeoffs and alternatives. In the CMOS technologies of the recent past where minimizing the die area was crucial, radix-4 minimally redundant SRT dividers were widely used because they only require simple multiples of divisor. Quotient conversion was typically done by on-the-fly conversion. In deep submicron CMOS technology these decisions need to be reconsidered. Now it is attractive to use maximum redundancy to simplify quotient selection. Replacing the on-the-fly conversion that operates on every cycle with an adder that operates only one cycle reduces the switching factor by the order of 29x for the conversion during a double precision division. This is significant because the onthe-fly conversion can consume 30% of the total energy of a divider. Furthermore, the quotient computation is sped up by the elimination of the big lookup table of minimally redundant SRT dividers. To illustrate this concept of trading extra hardware for improved power and speed and a simpler implementation, a radix-4 maximally redundant divider is designed and implemented in 65 nm CMOS technology using an ASIC flow and single, double and triple V T devices. Clock and data gating and data recirculation techniques are used to save power. Finally, a method to evaluate design alternatives for energy efficiency is proposed that takes into account the active power consumption, the inactive power consumption and the duty cycle.
2006 IEEE International Symposium on Signal Processing and Information Technology, 2006
This paper presents a proposal for design of radix 4 SRT dividers for single precision DSP in dee... more This paper presents a proposal for design of radix 4 SRT dividers for single precision DSP in deep submicron CMOS technology. Radix 4 dividers with minimal redundancy were used widely in the previous technologies where minimizing the die area was the top priority. This was done because these dividers only require simple multiples of divisor, and quotient conversion was typically done by on-the-fly conversion without the need for an adder. On the other hand, in the current deep submicron CMOS technology where many millions of transistors are available in a relatively small silicon area, it is attractive to use an adder and maximum redundancy to simplify quotient selection and conversion. Replacing the on-the-fly conversion that operates on every cycle by an adder that operates only one cycle reduces the switching factor by the order of 6x. This is significant because the on-the-fly conversion can consume 30% of the total energy of a divider. Furthermore, thanks to the elimination of the big lookup table intrinsic in minimally redundant SRT dividers, the quotient computation is sped up. To illustrate this concept of trading a little extra hardware for reduced power and increased speed in the deep submicron CMOS technology, a number of single precision radix 4 dividers with maximal redundancy are designed and implemented in 65 nm CMOS technology using an ASIC flow and triple VT devices. Clock and data gating and data recirculating techniques are used to save power. High VT devices are introduced to reduce leakage power. Finally, a novel method to evaluate different alternatives for energy efficiency is described along with the implementation results.