Vikas Agarwal - Academia.edu (original) (raw)
Papers by Vikas Agarwal
Journal of Asset Management, 2000
ABSTRACT This paper attempts to shed light on the `black box' called hedge funds via the ... more ABSTRACT This paper attempts to shed light on the `black box' called hedge funds via the style analysis technique developed by Sharpe (1992). The conventional style analysis cannot be directly applied to hedge funds as it imposes two constraints: first, the style weights have to be non-negative, and secondly, they have to add up to 100 per cent. In addition, the conventional style analysis does not provide any information about the statistical significance of the style weights. In this paper, we conduct a generalised style analysis of various hedge fund strategies by relaxing the constraints of the conventional style analysis, and examine the significance of style weights, as in Lobosco and DiBartolomeo (1997). We find that the generalised style analysis approach is more robust for estimating the risk exposures of hedge funds that take short positions in various asset classes and typically hold a significant part of their portfolio in cash.Journal of Asset Management (2000) 1, 93-109; doi:10.1057/palgrave.jam.2240007
SSRN Electronic Journal, 2000
SSRN Electronic Journal, 1999
Microprocessor performance has been improved by increasing the capacity of on-chip caches. Howeve... more Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption due to subthreshold leakage current. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy/performance trade-offs of these techniques and find that dynamic threshold modulation achieves the best results for level-1 caches, improving the energy-delay product by 2% in a level-1 instruction cache and 7% in a level-1 data cache. Low-leakage transistors perform best for the level-2 cache as they reduce static energy by up to 98% and improve the energy-delay product by more than a factor of 50.
In this report, we describe technology-driven models for wire capacitance, wire delay, and microa... more In this report, we describe technology-driven models for wire capacitance, wire delay, and microar-chitectural component delay. We used a 3D-field solver (Space3D) to generate our capacitance model based on technology parameters derived from the International ...
The doubling of microprocessor performance every three years has been the result of two factors: ... more The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance-estimating both clock rate and IPCof an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.
IEEE Transactions on Very Large Scale Integration Systems, 2003
Microprocessor performance has been improved by increasing the capacity of on-chip caches. Howeve... more Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.
... IBM, and Intel. References [1] MS Hrishikesh, NP Jouppi, KI Farkas, D. Burger, SW Keckler, an... more ... IBM, and Intel. References [1] MS Hrishikesh, NP Jouppi, KI Farkas, D. Burger, SW Keckler, and P. Shivakumar, The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays, ISCA-29, pp. 14-24, May, 2002. [2] R ...
The Journal of Alternative Investments, 2000
SSRN Electronic Journal, 2000
SSRN Electronic Journal, 2003
This paper investigates the determinants of money-flows, nature of managerial incentives, behavio... more This paper investigates the determinants of money-flows, nature of managerial incentives, behavior of investors, and drivers of performance in the hedge fund industry. It examines performance-flow relation and finds that funds with good recent performance, greater managerial incentives, and lower impediments to capital withdrawals experience higher money-flows. It also analyzes how current money-flows relate to future performance and finds that larger funds with greater inflows are associated with poorer future performance, a result consistent with decreasing returns to scale. It also finds that funds with greater managerial incentives are associated with superior future performance, justifying investors' preference for funds with higher managerial incentives. 5 Our finding of a convex performance-flow relation is consistent with that of , in the mutual fund industry.
This paper investigates the determinants of money-flows, nature of managerial incentives, behavio... more This paper investigates the determinants of money-flows, nature of managerial incentives, behavior of investors, and drivers of performance in the hedge fund industry. It examines performance-flow relation and finds that funds with good recent performance, greater managerial incentives, and lower impediments to capital withdrawals experience higher money-flows. It also analyzes how current money-flows relate to future performance and finds that larger funds with greater inflows are associated with poorer future performance, a result consistent with decreasing returns to scale. It also finds that funds with greater managerial incentives are associated with superior future performance, justifying investors' preference for funds with higher managerial incentives. 5 Our finding of a convex performance-flow relation is consistent with that of , in the mutual fund industry.
Journal of Asset Management, 2000
ABSTRACT This paper attempts to shed light on the `black box' called hedge funds via the ... more ABSTRACT This paper attempts to shed light on the `black box' called hedge funds via the style analysis technique developed by Sharpe (1992). The conventional style analysis cannot be directly applied to hedge funds as it imposes two constraints: first, the style weights have to be non-negative, and secondly, they have to add up to 100 per cent. In addition, the conventional style analysis does not provide any information about the statistical significance of the style weights. In this paper, we conduct a generalised style analysis of various hedge fund strategies by relaxing the constraints of the conventional style analysis, and examine the significance of style weights, as in Lobosco and DiBartolomeo (1997). We find that the generalised style analysis approach is more robust for estimating the risk exposures of hedge funds that take short positions in various asset classes and typically hold a significant part of their portfolio in cash.Journal of Asset Management (2000) 1, 93-109; doi:10.1057/palgrave.jam.2240007
SSRN Electronic Journal, 2000
SSRN Electronic Journal, 1999
Microprocessor performance has been improved by increasing the capacity of on-chip caches. Howeve... more Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption due to subthreshold leakage current. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy/performance trade-offs of these techniques and find that dynamic threshold modulation achieves the best results for level-1 caches, improving the energy-delay product by 2% in a level-1 instruction cache and 7% in a level-1 data cache. Low-leakage transistors perform best for the level-2 cache as they reduce static energy by up to 98% and improve the energy-delay product by more than a factor of 50.
In this report, we describe technology-driven models for wire capacitance, wire delay, and microa... more In this report, we describe technology-driven models for wire capacitance, wire delay, and microar-chitectural component delay. We used a 3D-field solver (Space3D) to generate our capacitance model based on technology parameters derived from the International ...
The doubling of microprocessor performance every three years has been the result of two factors: ... more The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance-estimating both clock rate and IPCof an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.
IEEE Transactions on Very Large Scale Integration Systems, 2003
Microprocessor performance has been improved by increasing the capacity of on-chip caches. Howeve... more Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.
... IBM, and Intel. References [1] MS Hrishikesh, NP Jouppi, KI Farkas, D. Burger, SW Keckler, an... more ... IBM, and Intel. References [1] MS Hrishikesh, NP Jouppi, KI Farkas, D. Burger, SW Keckler, and P. Shivakumar, The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays, ISCA-29, pp. 14-24, May, 2002. [2] R ...
The Journal of Alternative Investments, 2000
SSRN Electronic Journal, 2000
SSRN Electronic Journal, 2003
This paper investigates the determinants of money-flows, nature of managerial incentives, behavio... more This paper investigates the determinants of money-flows, nature of managerial incentives, behavior of investors, and drivers of performance in the hedge fund industry. It examines performance-flow relation and finds that funds with good recent performance, greater managerial incentives, and lower impediments to capital withdrawals experience higher money-flows. It also analyzes how current money-flows relate to future performance and finds that larger funds with greater inflows are associated with poorer future performance, a result consistent with decreasing returns to scale. It also finds that funds with greater managerial incentives are associated with superior future performance, justifying investors' preference for funds with higher managerial incentives. 5 Our finding of a convex performance-flow relation is consistent with that of , in the mutual fund industry.
This paper investigates the determinants of money-flows, nature of managerial incentives, behavio... more This paper investigates the determinants of money-flows, nature of managerial incentives, behavior of investors, and drivers of performance in the hedge fund industry. It examines performance-flow relation and finds that funds with good recent performance, greater managerial incentives, and lower impediments to capital withdrawals experience higher money-flows. It also analyzes how current money-flows relate to future performance and finds that larger funds with greater inflows are associated with poorer future performance, a result consistent with decreasing returns to scale. It also finds that funds with greater managerial incentives are associated with superior future performance, justifying investors' preference for funds with higher managerial incentives. 5 Our finding of a convex performance-flow relation is consistent with that of , in the mutual fund industry.