Wendem Beyene - Academia.edu (original) (raw)

Papers by Wendem Beyene

Electric Power Systems Research, 1996

For ship detection, X-band synthetic aperture radar (SAR) imagery provides very useful data, in t... more For ship detection, X-band synthetic aperture radar (SAR) imagery provides very useful data, in that ship targets look much brighter than surrounding sea clutter due to the corner-reflection effect. However, there are many phenomena which bring out false detection in the SAR image, such as noise of background, ghost phenomena, side-lobe effects and so on. Therefore, when ship-detection algorithms are carried out, we should consider these effects and mitigate them to acquire a better result. In this paper, we propose an efficient method to detect ship targets from X-band Kompsat-5 SAR imagery using the artificial neural network (ANN). The method produces the ship-probability map using ANN, and then detects ships from the ship-probability map by using a threshold value. For the purpose of getting an improved ship detection, we strived to produce optimal input layers used for ANN. In order to reduce phenomena related to the false detections, the non-local (NL)-means filter and median filter were utilized. The NL-means filter effectively reduced noise on SAR imagery without smoothing edges of the objects, and the median filter was used to remove ship targets in SAR imagery. Through the filtering approaches, we generated two input layers from a Kompsat-5 SAR image, and created a ship-probability map via ANN from the two input layers. When the threshold value of 0.67 was imposed on the ship-probability map, the result of ship detection from the ship-probability map was a 93.9% recall, 98.7% precision and 6.1% false alarm rate. Therefore, the proposed method was successfully applied to the ship detection from the Kompsat-5 SAR image.

2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2018

Silicon bridge is a promising solution that provides communication paths among multiple SoCs in a... more Silicon bridge is a promising solution that provides communication paths among multiple SoCs in a single package. It also provides a low-impedance path for the power delivery between two or more SoCs. However, a congested dense signal routing inside the silicon bridge makes the timing error worse. The switching noise on the power rail also increases the timing error of the interfaces. We investigated all possible sources of self-generated and coupled noise inside silicon bridge and analyzed the impact on the timing error.

2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2016

As the data rates increase rapidly in high speed systems — such as SerDes and memory systems — to... more As the data rates increase rapidly in high speed systems — such as SerDes and memory systems — to meet the bandwidth growth intensified by various applications, the electrical performance of packages has become critical. The bump and BGA or pin assignments, the layer stack up, and package material selection are very important to meet the signal and power integrity requirements. In addition, the role of new emerging 2.5D and 3D IC packaging platforms with ever increasing system integration requirements have made the role of packaging even more important. The sources of signal loss, noise coupling and discontinuities in packages must be fully understood and minimized when designing packages. At the same time, the design and development of packages have to meet cost, performance, form factor and reliability goals. In this talk we will examine the key electrical characteristics: signal loss, signal crosstalk, return loss, mode conversion, power integrity and other important factors nece...

2008 58th Electronic Components and Technology Conference, 2008

Abstract This paper analyzes the impact of standard and coreless packages on the overall high-spe... more Abstract This paper analyzes the impact of standard and coreless packages on the overall high-speed system performance for data rate beyond 20 Gbps. Instead of focusing on package electrical performance in isolation, we study the package impact on the system ...

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

Page 1. Statistical Simulation of SSO Noise in Multi-Gigabit Systems Wendemagegnehu T. Beyene, Am... more Page 1. Statistical Simulation of SSO Noise in Multi-Gigabit Systems Wendemagegnehu T. Beyene, Amir Amirkhany, Ali Abbasfar Rambus Inc., 4440 ElCamino Real, Los Altos, CA 94022 Tel: 650-947 5000, Fax: 650-947 5001 . ...

2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 2008

... Acknowledgements The author would like to thank Brian Leibowitz, Hae-ChangLee, Yohan Frans, a... more ... Acknowledgements The author would like to thank Brian Leibowitz, Hae-ChangLee, Yohan Frans, and Marko Aleksic from Rambus for many fruitful discussions on the design of continuous-time linear equalizers and I/O circuits. ...

2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 2008

The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interfa... more The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the ...

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 2011

Electrical Performance of Electronic Packaging,

With the rapid advance of silicon process technology, it is now possible to design I10 circuits t... more With the rapid advance of silicon process technology, it is now possible to design I10 circuits that operate at multi-gigabit data rates. Rambus' next generation memory interface technology, code-named Yellowstone, utilizes bi-directional low-swing Differential Rambus Signaling Level (DRSL) with a data transfer rate starting at 3.2 Gbpdpair and scalable to 6.4 Gbpdpair. This paper describes the design and modeling methodology used to develop the Yellowstone memory channel with conventional interconnect technologies. First, the advantages of point-to-point differential signaling are discussed. Then, the design issues associated with low-cost conventional printed circuit boards (PCBs) and packages are described. This is followed by a discussion of the modeling issues associated with high data-rate channel design. A design and modeling methodology is proposed to ensure the robust operation of the Yellowstone memory channel. Finally, to illustrate the validity of the proposed modeling methodology, channel models are correlated with actual hardware at both component and system level in both time and frequency domains.

2007 IEEE International Symposium on Circuits and Systems, 2007

ABSTRACT This paper presents a neural network approach of pole clustering techniques to construct... more ABSTRACT This paper presents a neural network approach of pole clustering techniques to construct compact models of high-order systems. The approach can be used to reduce the order of complex models of high-speed interconnect systems obtained from standard rational approximation. The reduction of the order and complexity of circuit models are essential to improve the efficiency and stability of the time-domain simulation in very large distributed systems. The proposed procedure uses the clustering capabilities of self-organizing maps of artificial neural networks. Self-clustering maps are very suitable to identify the pole distributions, and efficiently generate cluster centers and representative poles for the compact models. To illustrate the validity of the method, examples of frequency-domain simulation results of high-speed memory system are given

2007 IEEE Electrical Performance of Electronic Packaging, 2007

Although it is well understood that a band-limited passive system can be a source of deterministi... more Although it is well understood that a band-limited passive system can be a source of deterministic jitter, it is less obvious that the deterministic and random jitters generated by the clock or data source can be enhanced significantly by the passive channel. In this paper, modeling and simulation techniques to predict jitter enhancement across interconnect systems are presented. The conventional method of using SPICE to calculate output jitter is computationally expensive. Instead, the effect of channel on input jitter can be represented by jitter impulse response or jitter transfer function in time or frequency domains, respectively. These jitter characteristic functions can then be used to efficiently determine the increase in jitter as signal propagates across an interconnect system. The probability mass function of jitter impulse response can also be constructed to statistically predict the jitter enhancement at lower bit-error rate. Finally, the results form SPICE-based simulation and those obtained using the jitter characteristic functions are compared.

2006 IEEE Electrical Performane of Electronic Packaging, 2006

... Gigahertz Applications Hao Shi, Wendemagegnehu T. Beyene, Sam Khalili, and Chuck Yuan Rambus ... more ... Gigahertz Applications Hao Shi, Wendemagegnehu T. Beyene, Sam Khalili, and Chuck Yuan Rambus Inc. ... The drill size of the micro-vias is 60 umwith capture pad diameter of 100 um (except the 300 um landing pad in LI for probing). ...

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

I. Introduction The main memory for desktops, laptops, workstations and servers typically resides... more I. Introduction The main memory for desktops, laptops, workstations and servers typically resides on modules. With the adoption of multi-core architectures by the computing industry and with the new computing trend of virtualization, the demand for memory performance is ...

This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell B... more This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell Broadband Enginetrade (Cell BE) processor developed by Sony Corporation, Sony Computer Entertainment, Toshiba and IBM. A system co-design and co-analysis approach was applied where different components of the system are designed and analyzed simultaneously to allow trade-offs to be made to optimize system electrical characteristics at low overall system cost. The XDR memory interface circuit implemented in the Cell BE processor, the power delivery system design and analysis, and the interface statistical signal integrity analysis will be described to illustrate this design and analysis approach.

IEEE Transactions on Advanced Packaging, 2008

Applications of multilinear and waveform relaxation methods are presented for efficient transient... more Applications of multilinear and waveform relaxation methods are presented for efficient transient analysis of interconnect-dominated nonlinear networks. In this paper, two procedures that realize these well-known and fundamental theories in conventional circuit simulation tools are developed by taking advantage of the unique characteristics of interconnect networks. The multilinear theory uses the Volterra functional series to decompose the nonlinear network into multiple linear networks. Then, the solutions of the mildly nonlinear network are obtained from the linear combinations of sequences of responses of the decomposed linear networks. On the other hand, the waveform relaxation technique is used to solve networks with strong nonlinearity. The networks are partitioned into linear and nonlinear subnetworks and each subnetwork is solved iteratively using the waveform relaxation technique. Simplified analysis steps that give good insight into these techniques are also derived analytically. Finally, the accuracy and efficiency of the methods are verified with two examples.

IEEE Transactions on Advanced Packaging, 2009

Abstract As the input/output (I/O) data rate increases to several gigabits per second, determinin... more Abstract As the input/output (I/O) data rate increases to several gigabits per second, determining the performance of high-speed interfaces using conventional simulation and measurement techniques is becoming very challenging. The models of the interconnects ...

IEEE Transactions on Advanced Packaging, 2009

Electric Power Systems Research, 1996

For ship detection, X-band synthetic aperture radar (SAR) imagery provides very useful data, in t... more For ship detection, X-band synthetic aperture radar (SAR) imagery provides very useful data, in that ship targets look much brighter than surrounding sea clutter due to the corner-reflection effect. However, there are many phenomena which bring out false detection in the SAR image, such as noise of background, ghost phenomena, side-lobe effects and so on. Therefore, when ship-detection algorithms are carried out, we should consider these effects and mitigate them to acquire a better result. In this paper, we propose an efficient method to detect ship targets from X-band Kompsat-5 SAR imagery using the artificial neural network (ANN). The method produces the ship-probability map using ANN, and then detects ships from the ship-probability map by using a threshold value. For the purpose of getting an improved ship detection, we strived to produce optimal input layers used for ANN. In order to reduce phenomena related to the false detections, the non-local (NL)-means filter and median filter were utilized. The NL-means filter effectively reduced noise on SAR imagery without smoothing edges of the objects, and the median filter was used to remove ship targets in SAR imagery. Through the filtering approaches, we generated two input layers from a Kompsat-5 SAR image, and created a ship-probability map via ANN from the two input layers. When the threshold value of 0.67 was imposed on the ship-probability map, the result of ship detection from the ship-probability map was a 93.9% recall, 98.7% precision and 6.1% false alarm rate. Therefore, the proposed method was successfully applied to the ship detection from the Kompsat-5 SAR image.

2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2018

Silicon bridge is a promising solution that provides communication paths among multiple SoCs in a... more Silicon bridge is a promising solution that provides communication paths among multiple SoCs in a single package. It also provides a low-impedance path for the power delivery between two or more SoCs. However, a congested dense signal routing inside the silicon bridge makes the timing error worse. The switching noise on the power rail also increases the timing error of the interfaces. We investigated all possible sources of self-generated and coupled noise inside silicon bridge and analyzed the impact on the timing error.

2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2016

As the data rates increase rapidly in high speed systems — such as SerDes and memory systems — to... more As the data rates increase rapidly in high speed systems — such as SerDes and memory systems — to meet the bandwidth growth intensified by various applications, the electrical performance of packages has become critical. The bump and BGA or pin assignments, the layer stack up, and package material selection are very important to meet the signal and power integrity requirements. In addition, the role of new emerging 2.5D and 3D IC packaging platforms with ever increasing system integration requirements have made the role of packaging even more important. The sources of signal loss, noise coupling and discontinuities in packages must be fully understood and minimized when designing packages. At the same time, the design and development of packages have to meet cost, performance, form factor and reliability goals. In this talk we will examine the key electrical characteristics: signal loss, signal crosstalk, return loss, mode conversion, power integrity and other important factors nece...

2008 58th Electronic Components and Technology Conference, 2008

Abstract This paper analyzes the impact of standard and coreless packages on the overall high-spe... more Abstract This paper analyzes the impact of standard and coreless packages on the overall high-speed system performance for data rate beyond 20 Gbps. Instead of focusing on package electrical performance in isolation, we study the package impact on the system ...

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, 2014

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

Page 1. Statistical Simulation of SSO Noise in Multi-Gigabit Systems Wendemagegnehu T. Beyene, Am... more Page 1. Statistical Simulation of SSO Noise in Multi-Gigabit Systems Wendemagegnehu T. Beyene, Amir Amirkhany, Ali Abbasfar Rambus Inc., 4440 ElCamino Real, Los Altos, CA 94022 Tel: 650-947 5000, Fax: 650-947 5001 . ...

2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 2008

... Acknowledgements The author would like to thank Brian Leibowitz, Hae-ChangLee, Yohan Frans, a... more ... Acknowledgements The author would like to thank Brian Leibowitz, Hae-ChangLee, Yohan Frans, and Marko Aleksic from Rambus for many fruitful discussions on the design of continuous-time linear equalizers and I/O circuits. ...

2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 2008

The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interfa... more The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the ...

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 2011

Electrical Performance of Electronic Packaging,

With the rapid advance of silicon process technology, it is now possible to design I10 circuits t... more With the rapid advance of silicon process technology, it is now possible to design I10 circuits that operate at multi-gigabit data rates. Rambus' next generation memory interface technology, code-named Yellowstone, utilizes bi-directional low-swing Differential Rambus Signaling Level (DRSL) with a data transfer rate starting at 3.2 Gbpdpair and scalable to 6.4 Gbpdpair. This paper describes the design and modeling methodology used to develop the Yellowstone memory channel with conventional interconnect technologies. First, the advantages of point-to-point differential signaling are discussed. Then, the design issues associated with low-cost conventional printed circuit boards (PCBs) and packages are described. This is followed by a discussion of the modeling issues associated with high data-rate channel design. A design and modeling methodology is proposed to ensure the robust operation of the Yellowstone memory channel. Finally, to illustrate the validity of the proposed modeling methodology, channel models are correlated with actual hardware at both component and system level in both time and frequency domains.

2007 IEEE International Symposium on Circuits and Systems, 2007

ABSTRACT This paper presents a neural network approach of pole clustering techniques to construct... more ABSTRACT This paper presents a neural network approach of pole clustering techniques to construct compact models of high-order systems. The approach can be used to reduce the order of complex models of high-speed interconnect systems obtained from standard rational approximation. The reduction of the order and complexity of circuit models are essential to improve the efficiency and stability of the time-domain simulation in very large distributed systems. The proposed procedure uses the clustering capabilities of self-organizing maps of artificial neural networks. Self-clustering maps are very suitable to identify the pole distributions, and efficiently generate cluster centers and representative poles for the compact models. To illustrate the validity of the method, examples of frequency-domain simulation results of high-speed memory system are given

2007 IEEE Electrical Performance of Electronic Packaging, 2007

Although it is well understood that a band-limited passive system can be a source of deterministi... more Although it is well understood that a band-limited passive system can be a source of deterministic jitter, it is less obvious that the deterministic and random jitters generated by the clock or data source can be enhanced significantly by the passive channel. In this paper, modeling and simulation techniques to predict jitter enhancement across interconnect systems are presented. The conventional method of using SPICE to calculate output jitter is computationally expensive. Instead, the effect of channel on input jitter can be represented by jitter impulse response or jitter transfer function in time or frequency domains, respectively. These jitter characteristic functions can then be used to efficiently determine the increase in jitter as signal propagates across an interconnect system. The probability mass function of jitter impulse response can also be constructed to statistically predict the jitter enhancement at lower bit-error rate. Finally, the results form SPICE-based simulation and those obtained using the jitter characteristic functions are compared.

2006 IEEE Electrical Performane of Electronic Packaging, 2006

... Gigahertz Applications Hao Shi, Wendemagegnehu T. Beyene, Sam Khalili, and Chuck Yuan Rambus ... more ... Gigahertz Applications Hao Shi, Wendemagegnehu T. Beyene, Sam Khalili, and Chuck Yuan Rambus Inc. ... The drill size of the micro-vias is 60 umwith capture pad diameter of 100 um (except the 300 um landing pad in LI for probing). ...

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

I. Introduction The main memory for desktops, laptops, workstations and servers typically resides... more I. Introduction The main memory for desktops, laptops, workstations and servers typically resides on modules. With the adoption of multi-core architectures by the computing industry and with the new computing trend of virtualization, the demand for memory performance is ...

This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell B... more This paper describes the design and analysis of the 3.2 Gbps XDRtrade memory system of the Cell Broadband Enginetrade (Cell BE) processor developed by Sony Corporation, Sony Computer Entertainment, Toshiba and IBM. A system co-design and co-analysis approach was applied where different components of the system are designed and analyzed simultaneously to allow trade-offs to be made to optimize system electrical characteristics at low overall system cost. The XDR memory interface circuit implemented in the Cell BE processor, the power delivery system design and analysis, and the interface statistical signal integrity analysis will be described to illustrate this design and analysis approach.

IEEE Transactions on Advanced Packaging, 2008

Applications of multilinear and waveform relaxation methods are presented for efficient transient... more Applications of multilinear and waveform relaxation methods are presented for efficient transient analysis of interconnect-dominated nonlinear networks. In this paper, two procedures that realize these well-known and fundamental theories in conventional circuit simulation tools are developed by taking advantage of the unique characteristics of interconnect networks. The multilinear theory uses the Volterra functional series to decompose the nonlinear network into multiple linear networks. Then, the solutions of the mildly nonlinear network are obtained from the linear combinations of sequences of responses of the decomposed linear networks. On the other hand, the waveform relaxation technique is used to solve networks with strong nonlinearity. The networks are partitioned into linear and nonlinear subnetworks and each subnetwork is solved iteratively using the waveform relaxation technique. Simplified analysis steps that give good insight into these techniques are also derived analytically. Finally, the accuracy and efficiency of the methods are verified with two examples.

IEEE Transactions on Advanced Packaging, 2009

Abstract As the input/output (I/O) data rate increases to several gigabits per second, determinin... more Abstract As the input/output (I/O) data rate increases to several gigabits per second, determining the performance of high-speed interfaces using conventional simulation and measurement techniques is becoming very challenging. The models of the interconnects ...

IEEE Transactions on Advanced Packaging, 2009