News : Announcing Upcoming Special Sections Transactions on Advanced Packaging (original) (raw)
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Foreword Special Section on High-Speed I/O Channels
IEEE Transactions on Advanced Packaging, 2009
Modeling and analysis of high-speed links
2003
High-Speed Digital System Design—A Handbook of Interconnect Theory and Design Practices
Power-centric design of high-speed I/Os
Proceedings of the …, 2006
Design and modeling for chip-to-chip communication at 20 Gbps
2010
Signaling analysis of inter-chip I/O package routing for Multi-Chip Package
2012 4th Asia Symposium on Quality Electronic Design (ASQED), 2012
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$\mu$m CMOS Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
Frequency-dependent losses on high-performance interconnections
IEEE Transactions on Electromagnetic Compatibility, 2001
Substrate design optimization for high speed links
53rd Electronic Components and Technology Conference, 2003. Proceedings.
Design and modeling of a 3.2 Gbps/pair memory channel
Electrical Performance of Electronic Packaging,, 2002
Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009
Compact Models and Measurement Techniques for High-Speed Interconnects
2012
Guest Editors' Introduction: High-Performance Interconnects
IEEE Micro, 2000
The viability of 25 Gb/s on-board signalling
Dong Gun Kam, Christian Schuster
2008 58th Electronic Components and Technology Conference, 2008
A design methodology for the I/O power supply of next generation packaging
Electrical Performance of Electronic Packaging,
Significant of Signal Integrity in High Speed Board Design
Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication
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A 2.6-GByte/s multipurpose chip-to-chip interface
IEEE Journal of Solid-State Circuits, 1998
High-Speed Signaling in SDARM Bus Interface Channels : Review
2001
Information Technology Fibre Channel - High-Speed Parallel Interface
1999
Transmitter and channel equalization for high-speed server interconnects
IEEE Topical Meeting on Electrical Performance of Electronic Packaging, 2003
Statistical link analysis of high-speed memory I/O interfaces during simultaneous switching events
2008 IEEE-EPEP Electrical Performance of Electronic Packaging, 2008
Comparison of single and double channel I/O-configurations
Zeitschrift für Operations Research, 1984
Chain: a delay-insensitive chip area interconnect
IEEE Micro, 2002
Optimization of high‐speed VLSI interconnects: A review (invited article)
International Journal of Microwave and Millimeter‐Wave Computer‐Aided Engineering, 1997
Electrical design and layout rules for very high speed circuits
High Speed On-Chip Interconnects : Trade offs in Passive Termination
2008
Lumped-element sections for modeling coupling between high-speed digital and I/O lines
IEEE 1997, EMC, Austin Style. IEEE 1997 International Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.97CH36113), 1997