Yinpo Hung - Academia.edu (original) (raw)

Papers by Yinpo Hung

Microelectronics and Reliability, Nov 1, 2008

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutect... more A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn 3.0 Ag 0.5 Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260°C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young's modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.

2013 IEEE 63rd Electronic Components and Technology Conference, 2013

ABSTRACT In the evolution of IC package, the primary trend is regarded to be the upgrading from p... more ABSTRACT In the evolution of IC package, the primary trend is regarded to be the upgrading from planar 2D integration to 3D stacking. But before stepping into 3D IC category, a transitional generation called 2.5D is proposed. Due to the extremely fine pitch of modern IC, the IC substrate is difficult to match due to the incomparable line width/space. Therefore, a silicon interposer is introduced to fulfill the requirement of circuit re-distribution. In this paper, a package structure contains Si interposer to meet the demand of smaller and thinner form factor is proposed. The interposer is embedded into substrate by means of dielectric material lamination rather than solders joining and flip chip bonding. The embedded packaging technology is an integration of embedding active and passive components in built-up substrates and printed circuit boards (PCB). It can also be regarded as a process integration of PCB substrate and silicon substrate that raised the package density and miniaturized the package volume. In this investigation, an 8 inch thinned wafer was used as the test vehicle. Through silicon vias (TSVs) for interconnection could be produced either by deep reactive ion etching (DRIE) at wafer-level or by laser drilling at chiplevel. Meanwhile, Si chips were interconnected to the Si interposer to form an integrated 2.5D module. Afterwards, the 2.5D module was embedded by laminating a dielectric layer on both side of the module. Subsequently, the UV laser was used to form blind vias on the dielectric layer, and the chemical processes including de-smear, seed layer coating, Cu plating were applied to form the circuits or the BGA pads on the top or the bottom surface of build-up layer to connect the circuits of the 2.5D module. After circuit forming, the dielectric layer was fully cured at 170°C to enhance the adhesion between the Cu trace and the dielectric material. With this architecture, the thickness of interposer in a 2.5D-SiP could be subtracted, and the e- ectrical performance should be improved because of a shorter signal transmission route. The feasibility of the packaging structure has been verified. The reliability is assessing by preconditioning, and the results were also discussed here.

2008 58th Electronic Components and Technology Conference, 2008

In this paper, a construction of 3D array memory module based on chip-on-film (COF) bonding and c... more In this paper, a construction of 3D array memory module based on chip-on-film (COF) bonding and carrier stacking is developed. Experimental results are demonstrated on an 1.8&amp;amp;amp;amp;quot; HDD-identical platform, where the total thickness of the stacked 3D array memory module of 8 chips X 8 layers is less than 2 mm at 1.8&amp;amp;amp;amp;quot;-HDD area. All materials to implement this 3D

2008 58th Electronic Components and Technology Conference, 2008

... Li-Cheng Shen, Chien-Wei Chien, Jin-Ye Jaung, Yin-Po Hung, Wei-Chung Lo, Chao-Kai Hsu, Yuan-C... more ... Li-Cheng Shen, Chien-Wei Chien, Jin-Ye Jaung, Yin-Po Hung, Wei-Chung Lo, Chao-Kai Hsu, Yuan-Chang Lee *Hsien-Chie Cheng, *Chia-Te Lin ... the support from the MOEA Taiwan, ROC And also the technical support from Dr. Shu-Ming Chang, Mr. Ying-Ching Shih, Miss Shu ...

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference, 2010

... Tzu-Ying Kuo, Zhi-Cheng Hsiao, Yin-Po Hung, Wei Li, Kuo-Chyuan Chen, Chao-Kai Hsu, Cheng-Ta K... more ... Tzu-Ying Kuo, Zhi-Cheng Hsiao, Yin-Po Hung, Wei Li, Kuo-Chyuan Chen, Chao-Kai Hsu, Cheng-Ta Ko, Yu-Hua Chen ... 2nd Electronics Systemintegration Technology Conference, 2008, pp.125-130 [7] Ying-Ching Shih, et al, Manufacturing and Stacking of Ultra-Thin Film ...

2013 8th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013

ABSTRACT Chip embedded technology enables advanced integration of modern electronic package struc... more ABSTRACT Chip embedded technology enables advanced integration of modern electronic package structures due to its characteristics of small size, higher performance, lower overall cost and reduction of time to market. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. Comparing to 3D interconnection by through silicon via (TSV), device embedded module can have relevant effects by using PCB compatible process though the size and transmitting path is slightly higher than 3D IC modules. However, warpage issue is one of the significant factors that affect the manufacturing of device embedded products due to the asymmetric package form. A strong and robust substrate or core layer, such as high Tg FR4 substrate, BT substrate or Cu lead frame, is often required to provide a stiffening effect for the structure to prevent from severe warpage. In order to acquire even thinner package form, finer L/S specifications, and higher density of interconnection, coreless substrate may be one of the solution to meet the demand. But the asymmetric characteristic of embedded package structure may be regarded as a challenge when applied in coreless structure without a core layer. In this paper, a new type dielectric material with the characteristic of low CTE is disclosed. When it was applied in an asymmetric package structure with embedding chip, warpage behavior was found suppressed comparing to conventional dielectric materials. Moreover, when it was applied in a coreless structure with chip embedded, the structure can still maintain considerable flatness. The process feasibility of laser via forming, Cu plating was evaluated, while tensile strength of the plated Cu and reliability of the laminated structure were examined. An additional PI material was coated as the release layer in the forming of the coreless structure. The concept of asymmetric built-up coreless structure was brought up according to the materials' cha- acteristics and regarded as a potential solution for 3D System-in-Package in this study.

2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009

... Chih Chang1, Jin-Ye Juang1, Hung-Jen Chang2, Chun-Chih Chuang1, Chau-Jie Zhan1, Yin-Po Hung1,... more ... Chih Chang1, Jin-Ye Juang1, Hung-Jen Chang2, Chun-Chih Chuang1, Chau-Jie Zhan1, Yin-Po Hung1, Tsung-Fu Yang1, Wei Li 1 ... Afterwards, the PCBA test vehicles were underwent temperature cycling test and the real-time resistances of the daisy-chains were recorded by ...

2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2011

In this research, thousands of 20 μm pitch microbumps with a diameter of 10 μm and a structure of... more In this research, thousands of 20 μm pitch microbumps with a diameter of 10 μm and a structure of pure Sn cap on Cu pillar were electroplated on 8 inch wafers, and those wafers were then respectively singularized to be top chip (5 mm × 5 mm) and bottom Si interposer (10 mm × 10 mm) for stacking. Two methods including conventional reflow and solid-liquid interdiffusion (SLID) bonding were chosen to interconnect the microbumps on the chip and on the interposer. In the former case, the as-plated Sn caps were fluxed with Senju Metal's WF-6400 paste, and the chip was then placed on a Si interposer using a SÜSS FC-150 bonder at room temperature. Afterwards, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250°C in an ERSA's reflow oven (Hotflow 7). The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer were fully sealed by a Namics' capillary underfill with an average filler size of 0.3 um. Regarding the SLID bonding, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer by the SÜSS FC-150 bonder as well, subsequently, the Sn caps were heated up to 260°C to react with Cu to form Cu6Sn5 completely. In the final, the intermetallic microjoints were also protected by the same capillary underfill. After assembling, the JEDEC preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. According to the images of focus ion beam (FIB), the intermetallic phases of Cu6Sn5 and Cu3Sn coexisted at the interface between the Sn cap and the Cu pillar after reflow once, and some Kirkendall voids were found at the Cu3Sn / Cu pillar interface concurrently. When the microjoints undergone 3 times more reflow in the preconditioning test, the Kirkendall voids accumulated and was going to speed up the failure of microjoints as experienced just hundreds of temperature cycles. On the other hand, the microjoints produced by SLID bonding have not failed when thousands of temperature cycles passed. Based on those evidences, it is claimed here that SLID is an efficient bonding method to form reliable intermetallic microjoints for chip stacking.

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference, 2010

As high-speed, high-density, and high-performance are the primary IC development targets, packagi... more As high-speed, high-density, and high-performance are the primary IC development targets, packaging technologies play a key role to bring out the best performance of those ICs. In this paper, an active component formed by an active chip embedded technology is developed for the package of a high speed DDR2 memory device. Embedding of semiconductor chips into an organic substrate provide a solution to miniaturize the size of the package. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. In addition to wire bonding or w-BGA technologies, embedded package structure provides an alternative means to form redistribution circuits and electrical bonding pads. Meanwhile the electrical performance can be enhanced due to the wafer level package-like structure. Superior electrical performance is provided by forming shorter electrical path from chip pad to outer. In this study, a chip-in-substrate package (CiSP) with a real 50 um thick DDR2 memory IC is achieved using built-up technologies such as dielectric layer lamination, micro via drilling, and redistribution layer forming to implement the JEDECcompliant DDR2 component. The PCB compatible process is a lowcost, high-yield, and versatile technology. Electrical performance similar to wafer level package and even better than wire bonding or w-BGA package can be achieved by adopting this proposed solution. The DDR2 component is assembled on a dual in-line memory module (DIMM) to study the feasibility and electrical performance of this developed package. Subsequent reliability test such as thermal cycle test (TCT) and thermal humidity storage test (THST) are examined. And electromigration (EM) of this test vehicle under high current density is simulated and tested.

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011

Abstract This paper will highlight recent developments of an efficient assembly technology for ch... more Abstract This paper will highlight recent developments of an efficient assembly technology for chip stacking which utilizes a novel wafer applied underfill (WAUF). The a-stage WAUF was spin coated on an 8 wafer with a bump structure of 5 um Cu / 3 um Ni / 5 um Sn2.5Ag Pb-free ...

2009 59th Electronic Components and Technology Conference, 2009

... Ying-Ching Shih, Tzu-Ying Kuo, Yin-Po Hung, Jing-Yao Chang, Chih-Yuan Cheng, Kuo-Chyuan Chen,... more ... Ying-Ching Shih, Tzu-Ying Kuo, Yin-Po Hung, Jing-Yao Chang, Chih-Yuan Cheng, Kuo-Chyuan Chen, Ching-Kuan Lee, Chao-Kai Hsu, Jui-Hsiung Huang ... single UTFP can resist more than 200hrs under 5mm curvature radius and still does not have any change in electric ...

2007 Proceedings 57th Electronic Components and Technology Conference, 2007

... 2 (2000), pp.198-205. 2. Lau, JH, Low Cost Flip Chip Technologies: for DCA, WLCSP, and PBGA A... more ... 2 (2000), pp.198-205. 2. Lau, JH, Low Cost Flip Chip Technologies: for DCA, WLCSP, and PBGA Assemblies, McGraw-HillPrentice (New York, 2000), pp. 344-348. 584 2007 Electronic Components and Technology Conference

Journal of Adhesion Science and Technology, 2003

Adhesively bonded aluminum joints have been increasingly used in automotive industry because of t... more Adhesively bonded aluminum joints have been increasingly used in automotive industry because of their structural and functional advantages. Interfacial debonding in these joints has become a major concern limiting their performance. The present work is focused on experimental investigation of the influence of surface morphology on the interfacial fracture behavior of aluminum/epoxy interface. The specimens used in this experimental study were made of an aluminum/epoxy bimaterial stripe in the form of a layered double cantilever beam (LDCB). The LDCB specimens were debonded by peeling off the epoxy layer from the aluminum substrate using a steel wedge. Interfacial fracture energy was extracted from the debonding length by using a solution for the specimen geometry based on a model of a beam on an elastic foundation. This model was validated by direct finite element analysis. The experimental observations establish a direct correlation between the surface roughness of aluminum substrate and the fracture resistance of the aluminum/epoxy interface.

ABSTRACT In order to meet the demands for the high-density, high-performance, high-speed, smaller... more ABSTRACT In order to meet the demands for the high-density, high-performance, high-speed, smaller form factor and multi-function integration in portable electronic products, novel packaging technology now trends toward system in package (SiP) technology. 3D packaging technology is one of the most optimum means to achieve SiP. The embedded technology is one of the 3D packaging solutions and playing a key role to carry out the integration of heterogeneous devices. The embedded packaging technology addressed in this study was to bond an active device on a carrier substrate and then to achieve the "active embedded" package by laminating a dielectric material such as ABF on the substrate. The active embedded technology was successfully used to replace w-BGA to package a DDR2 device in ITRI [Ko et al.]. In the previous study, a real DDR2 IC with a thickness of 50 um was chosen to carry out ITRI's active embedded technology by wafer thinning, die bonding, ABF lamination, laser-via forming and electroplating via filling [IWLPC]. For simplifying the process flow, a new stackable embedding technology is developed to form a PoP module to extend the capacity of memory. In order to learn the reliability issues induced by the CTE mismatch of materials under temperature cyclic test, a simulation model was built-up to study the thermomechanical and stress concentration behaviors of the PoP module under TCT and to predict the life cycle times of the solder joints in the PoP module. The reliability characteristics of those two different interconnection structures would be assessed and compared. The embedded DRAM package devices had been accomplished and all samples had passed LV-3 pre-condition, TCT and THST reliability test. The thermal analysis of the stacking embedded DRAM package has been investigated using finite element modeling. Regarding the solder ball, the maximum Von Mises stress and plastic strain are located at outmost corner in the first solder. The fatigue lifetime of the maxi- - mum plastic strain solder is predicted as 1223 cycles. On the other hand, the Von Mises stress of the copper via in the ABF layer was larger than that in the substrate layer, indicating a possible failure site inside the package.