Yves Leduc - Academia.edu (original) (raw)

Papers by Yves Leduc

HAL (Le Centre pour la Communication Scientifique Directe), Oct 12, 2011

ESSCIRC 76: 2nd European Solid State Circuits Conference, 1976

Rapid Charge-Transfer in a saturated field effect transistor may be achieved by means of a feedba... more Rapid Charge-Transfer in a saturated field effect transistor may be achieved by means of a feedback loop. A sensitive on-chip amplifier for analog arrays was built using this principle.

IEEE Transactions on Electron Devices, 1979

An experimental and theoretical study of the three-terminal charge-injection device (3T-CID) oper... more An experimental and theoretical study of the three-terminal charge-injection device (3T-CID) operating as dynamic memory cell has been made. An optimized cell needs only about 60 percent of silicon surface compared to a classical single-transistor cell having the same storage capacitor. Several experimental arrays with minimum linewidth and spacing of 8 pm have been fabricated using an n-channel AI-gate LOCOS process with additional steps for the buried layers and contacts to them. The optimal operating voltages and the maximum charge that can be stored are influenced from the punchthrough voltage so that good control of the epitaxial process is necessary. Measurements at various arrays of 32 cells each and different cell sizes with minimum dimensions of 290 pm2 showed sufficiently large bitline signals, which can be further improved without an important loss of collector efficiency by the reduction of the bit-line width. In memories, however, lateral charge flow along the surface during injection is critical. Measurements showed an improvement if field shield lines and buried drain lines are used. LIST OF SYMBOLS Word-line voltage for writing. Word-line voltage for storage. Word-line voltage for punchthrough. Word-line voltage for reading. Flat-band voltage. Inversion charges per unit area. Space charges per unit area. Oxide capacitance per unit area. Bit-line potential of logical "1 ." Bit-line potential of logical "0." Thickness of the epitaxial layer. Electronic charge. Acceptor concentration in the epitaxial layer. Donator concentration in the buried layer. Boltzmann constant. Temperature, in kelvins. Richardson constant. Potential barrier between the buried layer and the surface.

HAL (Le Centre pour la Communication Scientifique Directe), Apr 16, 2012

International audienc

IEEE Electromagnetic Compatibility Magazine

HAL (Le Centre pour la Communication Scientifique Directe), Jun 11, 2012

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI tec... more In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors allows us to create a QRO (Quadrature Ring Oscillator) reducing both size and power consumption. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we can propose a low power ILCDR with low jitter and fast locking time for burst-mode applications. The main novelty consists in the implementation of a complementary QRO based on back-gate control using FDSOI technology in order to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (27 PRBS) at 868Mbps, the recovered clock jitter is 18.5 ps (1.6%UIp-p) and the recovered data jitter is 18.7 ps (1.6%UIp-p). With a 0.6 V power supply, the power consumption is 4.67 mA (2.8 mW). The estimated Chip size is around 6600 µm².

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016

An analog clock generator built with complementary logic cells in UTBB-FDSOI delivers the robust ... more An analog clock generator built with complementary logic cells in UTBB-FDSOI delivers the robust symmetrical clocks required to control high-performance differential switched-capacitor circuits. Using back-gate feedback and sizing respecting static and dynamic symmetry, the proposed solution is very tolerant to process inherent variations to the deep nanometer CMOS processes.

2018 International Conference on Computer and Applications (ICCA), 2018

In this paper, we present the design of a multiplier, an activation function and its derivative b... more In this paper, we present the design of a multiplier, an activation function and its derivative blocks to realize a neural network based on the Multi-Layer Perceptron with back propagation (MLP) algorithm. The network and the building blocks are validated using Simulink simulations. This is to help in the future to build the equivalent blocks in Analog CMOS circuits.

2017 29th International Conference on Microelectronics (ICM), 2017

This paper presents the design of a programmable signal generator to produce the inputs and the d... more This paper presents the design of a programmable signal generator to produce the inputs and the desired outputs to test an integrated circuit IC dedicated for neural network application (on chip learning). The main blocks for this design are a microcontroller PIC18F2680, a multiplexer 4067, and an LCD LM032L. The outputs of the programmable signal generator have an amplitude up to 1 V at a frequency up to 5 KHz, which is sufficient for our application, i.e. the breast cancer detection.

SN Applied Sciences, 2019

In this paper, we have implemented, using Matlab Simulink an analog artificial neural network for... more In this paper, we have implemented, using Matlab Simulink an analog artificial neural network for breast cancer classification. Simulated results with ideal building blocks exhibit a total error of classification of 2.6%. Thanks to this value, we have modified Simulink models of the building blocks (i.e. multiplier, activation function and its derivative) in order to take into account their non-idealities. This study allows to determine their influence on the classification quality and to extract some specifications of these building blocks.

J3eA, 2019

Pour poursuivre la loi de Moore avec des noeuds technologiques de 22 nm et en deçà, les transisto... more Pour poursuivre la loi de Moore avec des noeuds technologiques de 22 nm et en deçà, les transistors MOS bulk ont été remplacés par des transistors FinFET ou UTBB-FDSOI. Ces derniers disposent d’une grille arrière permettant de réaliser de nouvelles topologies de circuits analogiques et mixtes, offrant des performances jamais atteintes et réduisant certaines limitations, comme par exemple celles liées à la réduction de la longueur du canal. Partant de la caractéristique de la tension de seuil d’un transistor UTBB-FDSOI en fonction de la polarisation de la grille arrière, nous proposons aux élèves-ingénieurs d’étudier quelques nouvelles topologies de cellules par des simulations statiques et transitoires, associés à des analyses de Monte Carlo pour évaluer l’impact des variations du procédé de fabrication sur leurs performances finales. La première étude concerne la réalisation d’un inverseur en logique complémentaire basé sur le couplage croisé des grilles arrières de deux inverseurs...

Journal of Low Power Electronics, 2016

2015 International Workshop on CMOS Variability (VARI), 2015

This In this paper, we present a new inverter topology in order to decrease the process variabili... more This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary cells allow us to implement back-gate auto-biasing feedback without adding transistors and to realize a quadrature ring oscillator with an even number of inverters.