A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications (original) (raw)
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A pattern-dependent injection-locked CDR for clock-embedded signaling
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This paper presents a CDR architecture for clock-embedded signaling. To suppress the effect of data-dependent jitter of the conventional DLL-based approach, we propose a pattern-dependent injection-locking scheme in a PLL-based clock recovery circuit. It achieves both benefits of PLL and DLL, the input jitter filtering and the clearance of accumulated VCO jitter, respectively. A jitter analysis is also presented to develop a design strategy for the optimal extraction of injection timing from random data stream. The CDR, implemented in a 28 nm CMOS, achieves a data rate of 12.5 Gb/s with a 13.7 dB-loss channel and verifies the validity of the analysis.
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In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18-μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4-mW and minimum 2.6-mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak-to-peak jitter is equal to 5.17 ps, and its minimum peak-to-peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively. KEYWORDS charge pump, delay locked loop, frequency range, jitter, voltage controlled delay line 1 | INTRODUCTION Delay locked loops (DLLs) have first-order control systems. DLLs are similar to phase locked loops (PLLs) in many aspects, and they are being used a lot in microprocessors and memories. DLLs can be used where stability, jitter performance, and occupied chip area are important. 1 The performance of a DLL depends on many assistant parameters including static phase error, lock time, lock range, and jitter. Static phase error is the phase difference between output signal of last stage of VCDL and input reference signal in lock mode. Lock time is the duration in which a DLL reaches stable lock mode with respect to its initial condition. Lock range in DLL is actually the range between minimum and maximum delays in a VCDL, and it directly affects DLL operating frequency range. Lock range can increase in a VCDL through increasing delay cells. In other words, delay range implies frequency range which a DLL can lock. 2 The small and random variations in output signal are called jitter. DLLs show better jitter performance in comparison with PLLs. 3 Nowadays, DLLs with wide frequency range and low power are of high importance in mobile applications. In addition, using frequency synthesizers and multipliers based on DLLs has increased frequency range remarkably. A