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Papers by anil kumar rajput

Research paper thumbnail of Low Noise Amplifier for Health Monitoring

2021 IEEE Bombay Section Signature Conference (IBSSC), 2021

This paper presents a low-noise low-power operational amplifier circuit to amplify bio-medical si... more This paper presents a low-noise low-power operational amplifier circuit to amplify bio-medical signals at low frequency. Complementary based differential input technique with large transistor is used to reduce the input referred noise. Class-AB technique is used at the output stage to increase the voltage swing and to enhance the gm/ID efficiency. Control circuitry of class-AB structure is fixed into the differential stage to minimize the power consumption. SCL-PDK library at 180nm is used to analyze the amplifier circuit. The proposed circuit reduces the noise and power consumption of the amplifier by 44% and 72% with increase of gain-bandwidth product by 8% at the cost of reduced ICMR by 4% when compared to recently reported amplifiers.

Research paper thumbnail of Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation

2020 International Conference for Emerging Technology (INCET), 2020

The current computing system based on von-Neumann architecture is facing a memory wall, power wal... more The current computing system based on von-Neumann architecture is facing a memory wall, power wall, instruction parallelism wall. These walls of the current computing system have been a significant impact on computing efficiency of computing systems in the present time due to high prominence on Data insensitive applications. Computation In Memory (CIM) architecture is one of the emerging architecture for computation to break these three walls. In this paper, we present an In memory computational methodology and arithmetic circuit co- designs using 8T SRAM cell. The boolean logic operation and arithmetic functions are demonstrated with 8T SRAM cell in 180 nm CMOS technology. The NAND, AND, NOR, OR boolean logics are demonstrate using 8T SRAM cells with the proposed sensing scheme to verifying the In-Memory computations ability of 8T SRAM cells. This proposed sensing scheme with 8T SRAM cell provides an energy improvement of 26.4% over 8+T SRAM based IMC and also offer a high sense margin of NAND operation. Finally, for implementation of the arithmetic circuit, SRAM memory array has to be designed using the 8T SRAM cell and proposed sensing scheme and mapped half adder and half subs tractor NOR net-list into SRAM memory array and verify their functionality.

Research paper thumbnail of Low Power Boolean Logic Circuits using Reversible Logic Gates

2019 International Conference on Advances in Computing, Communication and Control (ICAC3), 2019

Low power design is a promising characteristic for the application ranging from the Internet of t... more Low power design is a promising characteristic for the application ranging from the Internet of things (IoTs) to quantum computing. The boolean logic based on the reversible concept is the emerging technology for low power digital logic circuit design for quantum computing application. The reversible logic circuit provides an entirely new way of processing quantum computing. In this paper,we present the transistor level implementation of state-of-the-art reversible gates and proposed boolean logic circuits using reversible logic gates. The various Boolean logic circuits based on reversible logic gates are designed using the SCL180nm library. Furthers, we introduced D-flip flop and 4×1 MUX using the reversible gate, which has an energy efficiency of 14% and 94%, respectively, with reported paper. This proposed logic circuits achieved area efficiency as well as a power-efficiency because of reversible logic gates, which consume less power due to its distinctive input-output mapping te...

Research paper thumbnail of Performance Analysis of Dual Metal Nitride Oxide GAAFET based Common Source Amplifier

Gate all around FET (GAAFET) is a widely used device structure for designing analog and digital c... more Gate all around FET (GAAFET) is a widely used device structure for designing analog and digital circuits. In this research paper, a common source amplifier is designed using a dual-metal nitride oxide gate all around FET (DM-NO GAAFET), and performance is investigated for gain, bandwidth, leakage power, and average power. Moreover, analytical expressions of potential, threshold voltage, and DIBL have also been given for DM-NO GAAFET. The DM-NO GAAFET based common source (CS) amplifier is compared with the MOSFET based CS amplifier to analyse the performance. First, RF performance parameters of total gate capacitance, unity gain frequency, and transit time are investigated for DM-NO GAAFET; consequently, look up table based Verilog A model is used to design CS amplifier. Since DM-NO GAAFET provides the very small value of miller capacitance which increases the maximum unity gain frequency of 2.340 THz at the gate voltage of 0.7V. The voltage gain of 2.51 at the frequency range of 10H...

Research paper thumbnail of Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation

2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

The state-of-the-art computing systems based on traditional von-Neumann architectures are facing ... more The state-of-the-art computing systems based on traditional von-Neumann architectures are facing von-Neumann bottlenecks(VNB), which has large impact on computing speed and energy consumption of current computing system for big-data applications. Computation-In-Memory (CIM) architecture is prominent candidate for computation to break VNB. In this paper, we propose a 9T (P9T) SRAM bit-cell that is energy efficient and at the same time, it enhances the read/write margin. The simulation result shows that the P9 TTT SRAM design increases Read SNM (RSNM), Write SNM (WSNM), Dynamic noise margin (DNM) and Ion/Ioff by 25.44%,19.44%,56.41% and 102.5%, respectively at 1.8V supply voltage over Conventional 8T (C8T) SRAM cell in a 180nm CMOS technology. The P9T SRAM design decrease read and write energy per operation by 60.85% and 22.67%, respectively over the C8T SRAM bit-cell. Finally for illustration of beyond von-Neumann computation, the In-memory Boolean Computation (IMBC) operation has be...

Research paper thumbnail of Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

In the research paper, the semi-analytical modelling is done for low drain-induced barrier loweri... more In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.

Research paper thumbnail of Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard

In order to support real-time HD video requirements for mobile and real time applications, energy... more In order to support real-time HD video requirements for mobile and real time applications, energy-efficient design is the need of the hour for such low-cost devices. HEVC is the latest video compression standard that achieves high compression ratio and high bit-rate over existing architecture(H.264) but at the cost of higher computational complexity. HEVC incorporates integer DCT as an essential transform scheme for compressing the successive video frames. Approximate Integer DCT implementations with quality as a major constraint are proposed which consider the properties of transform matrices as prescribed by HEVC. A systematic approximation strategy has been introduced to achieve a reasonable quality-energy trade-off. The proposed 1-D architectures have reduced arithmetic complexity and less hardware resources when implemented on Artix-7 FPGA. A 56% reduction in resource utilization and 62% reduction in ASIC power when implemented on CMOS 180 nm technology is obtained compared wit...

Research paper thumbnail of Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems

IEEE Consumer Electronics Magazine, 2019

he ever-increasing demand for in-home products, automation, and sharing information over social n... more he ever-increasing demand for in-home products, automation, and sharing information over social networks has opened a gateway for consumer electronics (CE) devices. As a result, system on chip (SoC)-based multiprocessor systems are designed to meet the current demand. This article presents the architectural issues of multiprocessor SoCs (MPSoCs) used in CE devices and provides network on chip (NoC)-based multiprocessors as a solution that helps alleviate the performance of CE devices. Asynchronous NoC propounds more throughput and lower latency than synchronous NoC for a specific number of virtual channels (VCs) and cores. Network on Chip for Consumer Electronics Devices An architectural and performance exploration of synchronous and asynchronous network-on-chip-based systems.

Research paper thumbnail of Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip

2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016

This paper presents a comparison of throughput and end-to-end latency of synchronous and asynchro... more This paper presents a comparison of throughput and end-to-end latency of synchronous and asynchronous heterogeneous NoC under uniform and exponential traffic conditions using different parameters. The parameters we have chosen are no. of cores, load (traffic) and no. of VCs of a router. Further, sink bandwidth analysis of synchronous and asynchronous NoC under uniform traffic was studied and compared. The experimental results show that asynchronous NoC offers more bandwidth, high throughput and low latency than the synchronous NoC for a given no. of VCs and cores.

Research paper thumbnail of GAAFET based SRAM Cell to Enhance Stability for Low Power Applications

Silicon, 2022

This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6... more This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6 T and 7 T SRAM cells on enhancing stability for low power applications. GAAFETs are used in cross-coupled inverter circuitry to increase the stability of proposed 6 T and 7 T SRAM cells as these cross-coupled inverters provide the closest ideal voltage transfer characteristics (VTC) due to the earlier saturation effect. The calibration of the simulation setup has also been done in this paper before using GAAFET in SRAM cell design. Moreover, the Look-up table-based Verilog A approach is adopted in the paper for device circuit co-design. Proposed 6 T SRAM cell is analysed for the performance metrics like read static noise margin (RSNM), write margin (WM), read delay, write delay, read power and write power at various supply voltages (VDD) and further be improved to the proposed 7 T SRAM cell. The proposed 7 T SRAM enhances RSNM and WM by 55.56% and 24.60%, respectively, and also reduces read and write power consumption by 6.50% and 88.76%, respectively, as compared to DP-DGTFET based 7 T SRAM cell at VDD = 0.6 V. Furthermore, proposed 7 T SRAM reduces read and write delay by 62.95% and 74.93% respectively at VDD = 0.6 V as well. The power gating technique is used in the proposed 7 T SRAM to reduce leakage power by 37.18%, and 80.81% compared to the 6 T CMOS SRAM and proposed GAAFET based 6 T SRAM cell, respectively. Therefore, the proposed 7 T SRAM cell could be used for high stability and low power applications.

Research paper thumbnail of Low Noise Amplifier for Health Monitoring

2021 IEEE Bombay Section Signature Conference (IBSSC), 2021

This paper presents a low-noise low-power operational amplifier circuit to amplify bio-medical si... more This paper presents a low-noise low-power operational amplifier circuit to amplify bio-medical signals at low frequency. Complementary based differential input technique with large transistor is used to reduce the input referred noise. Class-AB technique is used at the output stage to increase the voltage swing and to enhance the gm/ID efficiency. Control circuitry of class-AB structure is fixed into the differential stage to minimize the power consumption. SCL-PDK library at 180nm is used to analyze the amplifier circuit. The proposed circuit reduces the noise and power consumption of the amplifier by 44% and 72% with increase of gain-bandwidth product by 8% at the cost of reduced ICMR by 4% when compared to recently reported amplifiers.

Research paper thumbnail of Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation

2020 International Conference for Emerging Technology (INCET), 2020

The current computing system based on von-Neumann architecture is facing a memory wall, power wal... more The current computing system based on von-Neumann architecture is facing a memory wall, power wall, instruction parallelism wall. These walls of the current computing system have been a significant impact on computing efficiency of computing systems in the present time due to high prominence on Data insensitive applications. Computation In Memory (CIM) architecture is one of the emerging architecture for computation to break these three walls. In this paper, we present an In memory computational methodology and arithmetic circuit co- designs using 8T SRAM cell. The boolean logic operation and arithmetic functions are demonstrated with 8T SRAM cell in 180 nm CMOS technology. The NAND, AND, NOR, OR boolean logics are demonstrate using 8T SRAM cells with the proposed sensing scheme to verifying the In-Memory computations ability of 8T SRAM cells. This proposed sensing scheme with 8T SRAM cell provides an energy improvement of 26.4% over 8+T SRAM based IMC and also offer a high sense margin of NAND operation. Finally, for implementation of the arithmetic circuit, SRAM memory array has to be designed using the 8T SRAM cell and proposed sensing scheme and mapped half adder and half subs tractor NOR net-list into SRAM memory array and verify their functionality.

Research paper thumbnail of Low Power Boolean Logic Circuits using Reversible Logic Gates

2019 International Conference on Advances in Computing, Communication and Control (ICAC3), 2019

Low power design is a promising characteristic for the application ranging from the Internet of t... more Low power design is a promising characteristic for the application ranging from the Internet of things (IoTs) to quantum computing. The boolean logic based on the reversible concept is the emerging technology for low power digital logic circuit design for quantum computing application. The reversible logic circuit provides an entirely new way of processing quantum computing. In this paper,we present the transistor level implementation of state-of-the-art reversible gates and proposed boolean logic circuits using reversible logic gates. The various Boolean logic circuits based on reversible logic gates are designed using the SCL180nm library. Furthers, we introduced D-flip flop and 4×1 MUX using the reversible gate, which has an energy efficiency of 14% and 94%, respectively, with reported paper. This proposed logic circuits achieved area efficiency as well as a power-efficiency because of reversible logic gates, which consume less power due to its distinctive input-output mapping te...

Research paper thumbnail of Performance Analysis of Dual Metal Nitride Oxide GAAFET based Common Source Amplifier

Gate all around FET (GAAFET) is a widely used device structure for designing analog and digital c... more Gate all around FET (GAAFET) is a widely used device structure for designing analog and digital circuits. In this research paper, a common source amplifier is designed using a dual-metal nitride oxide gate all around FET (DM-NO GAAFET), and performance is investigated for gain, bandwidth, leakage power, and average power. Moreover, analytical expressions of potential, threshold voltage, and DIBL have also been given for DM-NO GAAFET. The DM-NO GAAFET based common source (CS) amplifier is compared with the MOSFET based CS amplifier to analyse the performance. First, RF performance parameters of total gate capacitance, unity gain frequency, and transit time are investigated for DM-NO GAAFET; consequently, look up table based Verilog A model is used to design CS amplifier. Since DM-NO GAAFET provides the very small value of miller capacitance which increases the maximum unity gain frequency of 2.340 THz at the gate voltage of 0.7V. The voltage gain of 2.51 at the frequency range of 10H...

Research paper thumbnail of Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation

2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

The state-of-the-art computing systems based on traditional von-Neumann architectures are facing ... more The state-of-the-art computing systems based on traditional von-Neumann architectures are facing von-Neumann bottlenecks(VNB), which has large impact on computing speed and energy consumption of current computing system for big-data applications. Computation-In-Memory (CIM) architecture is prominent candidate for computation to break VNB. In this paper, we propose a 9T (P9T) SRAM bit-cell that is energy efficient and at the same time, it enhances the read/write margin. The simulation result shows that the P9 TTT SRAM design increases Read SNM (RSNM), Write SNM (WSNM), Dynamic noise margin (DNM) and Ion/Ioff by 25.44%,19.44%,56.41% and 102.5%, respectively at 1.8V supply voltage over Conventional 8T (C8T) SRAM cell in a 180nm CMOS technology. The P9T SRAM design decrease read and write energy per operation by 60.85% and 22.67%, respectively over the C8T SRAM bit-cell. Finally for illustration of beyond von-Neumann computation, the In-memory Boolean Computation (IMBC) operation has be...

Research paper thumbnail of Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

In the research paper, the semi-analytical modelling is done for low drain-induced barrier loweri... more In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.

Research paper thumbnail of Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard

In order to support real-time HD video requirements for mobile and real time applications, energy... more In order to support real-time HD video requirements for mobile and real time applications, energy-efficient design is the need of the hour for such low-cost devices. HEVC is the latest video compression standard that achieves high compression ratio and high bit-rate over existing architecture(H.264) but at the cost of higher computational complexity. HEVC incorporates integer DCT as an essential transform scheme for compressing the successive video frames. Approximate Integer DCT implementations with quality as a major constraint are proposed which consider the properties of transform matrices as prescribed by HEVC. A systematic approximation strategy has been introduced to achieve a reasonable quality-energy trade-off. The proposed 1-D architectures have reduced arithmetic complexity and less hardware resources when implemented on Artix-7 FPGA. A 56% reduction in resource utilization and 62% reduction in ASIC power when implemented on CMOS 180 nm technology is obtained compared wit...

Research paper thumbnail of Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems

IEEE Consumer Electronics Magazine, 2019

he ever-increasing demand for in-home products, automation, and sharing information over social n... more he ever-increasing demand for in-home products, automation, and sharing information over social networks has opened a gateway for consumer electronics (CE) devices. As a result, system on chip (SoC)-based multiprocessor systems are designed to meet the current demand. This article presents the architectural issues of multiprocessor SoCs (MPSoCs) used in CE devices and provides network on chip (NoC)-based multiprocessors as a solution that helps alleviate the performance of CE devices. Asynchronous NoC propounds more throughput and lower latency than synchronous NoC for a specific number of virtual channels (VCs) and cores. Network on Chip for Consumer Electronics Devices An architectural and performance exploration of synchronous and asynchronous network-on-chip-based systems.

Research paper thumbnail of Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on Chip

2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016

This paper presents a comparison of throughput and end-to-end latency of synchronous and asynchro... more This paper presents a comparison of throughput and end-to-end latency of synchronous and asynchronous heterogeneous NoC under uniform and exponential traffic conditions using different parameters. The parameters we have chosen are no. of cores, load (traffic) and no. of VCs of a router. Further, sink bandwidth analysis of synchronous and asynchronous NoC under uniform traffic was studied and compared. The experimental results show that asynchronous NoC offers more bandwidth, high throughput and low latency than the synchronous NoC for a given no. of VCs and cores.

Research paper thumbnail of GAAFET based SRAM Cell to Enhance Stability for Low Power Applications

Silicon, 2022

This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6... more This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6 T and 7 T SRAM cells on enhancing stability for low power applications. GAAFETs are used in cross-coupled inverter circuitry to increase the stability of proposed 6 T and 7 T SRAM cells as these cross-coupled inverters provide the closest ideal voltage transfer characteristics (VTC) due to the earlier saturation effect. The calibration of the simulation setup has also been done in this paper before using GAAFET in SRAM cell design. Moreover, the Look-up table-based Verilog A approach is adopted in the paper for device circuit co-design. Proposed 6 T SRAM cell is analysed for the performance metrics like read static noise margin (RSNM), write margin (WM), read delay, write delay, read power and write power at various supply voltages (VDD) and further be improved to the proposed 7 T SRAM cell. The proposed 7 T SRAM enhances RSNM and WM by 55.56% and 24.60%, respectively, and also reduces read and write power consumption by 6.50% and 88.76%, respectively, as compared to DP-DGTFET based 7 T SRAM cell at VDD = 0.6 V. Furthermore, proposed 7 T SRAM reduces read and write delay by 62.95% and 74.93% respectively at VDD = 0.6 V as well. The power gating technique is used in the proposed 7 T SRAM to reduce leakage power by 37.18%, and 80.81% compared to the 6 T CMOS SRAM and proposed GAAFET based 6 T SRAM cell, respectively. Therefore, the proposed 7 T SRAM cell could be used for high stability and low power applications.