idzdihar idris - Academia.edu (original) (raw)

Papers by idzdihar idris

Background: Integrated circuits are tested in final step of IC packaging to verify that required ... more Background: Integrated circuits are tested in final step of IC packaging to verify that required electrical connections are working properly. At present, Pogo Pins are used as electrical connection between IC lead and load board. Pogo pins caused different problems including indentation marks, blur marks, tilting, spring malfunction, high maintenance cost and etc. The present miniaturization trends towards higher performance, smaller and lighter product have resulted in an increasing demand for smaller pitch size and increase the issues of testing process with pogo pins. Pogo pins induced reliability problems when dealing with fine-pitch (< 0.5 mm) packages. New electrical conductive cell was designed in previous works. It was based on microstructures instead of pogo pins and consists of three different parts including polymer, metallic micro contactors and liquid metal. New Model was designed for QFP packages with 0.5 mm pitch size using simulation in previous years. Novel test ...

Fingerprint is a biometric that provides secure method to authenticate a person due to its perman... more Fingerprint is a biometric that provides secure method to authenticate a person due to its permanent feature and uniqueness that remain throughout human life. It has been in used for more than 100 years as a result of its feasibility, accuracy, reliability, and acceptability. Although there exist many algorithms for fingerprint authentication, there is still a need to close the gap of accurateness. Among the algorithm fingerprint methods are minutiae matching and pattern matching method. A minutiae matching is widely used for fingerprint recognition and can be classified as ridge ending and ridge bifurcation. In this paper the minutiae extraction method was improved by combining it with image enhancement that includes noise reduction, smoothing, contrast stretching, histogram equalization, Fourier transform and edge enhancement. This method presented a reasonable performance that gives a recognition rate up to 96.7% accuracy under supervised training fingerprint images.

2013 IEEE International Conference on RFID-Technologies and Applications (RFID-TA), 2013

ABSTRACT RFID is a worldwide attractive technology for reliable wireless communication system. Au... more ABSTRACT RFID is a worldwide attractive technology for reliable wireless communication system. Automatic gain control system of such devices is very important which is performed by Variable Gain Amplifier (VGA). In this paper, a class AB VGA, consisting of a linear transconductor amplifier and a linear transimpedance amplifier, is designed and simulated in CEDEC (software for design and simulation of ICs) 0.18-µm CMOS process for low power and high speed RFID receivers. The simulation result show that, the proposed VGA has a wide bandwidth of 100 MHz and dissipates power less than 125uW at 1V supply voltage. From the results it is also apparent that the circuit is capable of working with high linearity and wide bandwidth. Good frequency response (Gain) and the wide bandwidth of this class AB VGA makes it suitable for low power RFID receiver transceivers.

Advanced Materials Research, 2013

This paper presents a method based on statistical approach which known as Taguchi method. This me... more This paper presents a method based on statistical approach which known as Taguchi method. This method is used to optimize power dissipations and gain in a two-stage op-amp. Standard L27 which uses three factors and two outputs is chosen to optimize power and gain in the circuit. Simulation of the circuit has been implemented by using Mentor Graphics DA-IC. From the simulation, the results showed that total power dissipation has decreased from 3.9643 mW to 1.0345 mW. The percentage of power reduction is 73.9%. The overall gain also has been improved from 22 dB to 45.49 dB. The percentage of increment gain in two-stage op-amp is 56%.

ICSCRM2019 Organizing Committee, Sep 3, 2019

The effect of surface treatments prior to the deposition of Al2O3is performed on 4H-SiC MOS capac... more The effect of surface treatments prior to the deposition of Al2O3is performed on 4H-SiC MOS capacitors and MOSFETs. 40 nm of Al2O3were deposited on 4H-SiC using atomic layer deposition (ALD) as a gate dielectric. Different surface treatments were used to investigate the capacitance-voltage and current-voltage characteristics on MOS capacitors and MOSFETs respectively, including the important parameters such as interface state density, flat band voltage, threshold voltage and field-effect mobility. Forming gas annealing and rapid oxidation processes were found to be effective in reducing the interface state density and results in high field-effect mobility with peak field-effect mobility of 130 cm2Vs-1. The experimental results obtained manifest that the surface treatment prior to Al2O3deposition is critical to producing high performance of 4H-SiC MOSFETs.

Crystals

Enhancement-mode 4H-SiC MOSFETs utilising an aluminium oxide (Al2O3) dielectric without the requi... more Enhancement-mode 4H-SiC MOSFETs utilising an aluminium oxide (Al2O3) dielectric without the requirement for an underlying silicon oxide (SiO2) layer have been shown to have a field effect mobility of 150 cm2V−1s−1 and a subthreshold swing of 160 mV/dec. The fabricated devices utilised a forming gas (3% H2 in N2) anneal immediately prior to the deposition of the Al2O3 by Atomic Layer Deposition (ALD). A comparison MOSFET using an identical Al2O3 deposition process with a 0.7 nm SiO2 layer had a field effect mobility of approximately 20 cm2V−1s−1. The hydrogen annealed device had a lower density of interface traps (Dit), a lower subthreshold swing, and a significantly reduced hysteresis in the transconductance data than the thin SiO2 sample. This finding solves the issue of inconsistency of device performance using thin film gate dielectric as an interfacial layer by offering a simple and controllable process.

Materials Science Forum

The effect of surface treatments prior to the deposition of Al2O3 is performed on 4H-SiC MOS capa... more The effect of surface treatments prior to the deposition of Al2O3 is performed on 4H-SiC MOS capacitors and MOSFETs. 40 nm of Al2O3 were deposited on 4H-SiC using atomic layer deposition (ALD) as a gate dielectric. Different surface treatments were used to investigate the capacitance-voltage and current-voltage characteristics on MOS capacitors and MOSFETs respectively, including the important parameters such as interface state density, flat band voltage, threshold voltage and field-effect mobility. Forming gas annealing and rapid oxidation processes were found to be effective in reducing the interface state density and results in high field-effect mobility with peak field-effect mobility of 130 cm2Vs-1. The experimental results obtained manifest that the surface treatment prior to Al2O3 deposition is critical to producing high performance of 4H-SiC MOSFETs.

Journal of Robotics and Control (JRC)

The Delta robot is one of the robot types that is used in agriculture and industrial application.... more The Delta robot is one of the robot types that is used in agriculture and industrial application. However, before the complex physical development of the robot, a simulation needs to be developed to ensure the perfect functionality of the design. Therefore, this paper presented a development of simulation for a parallel delta robot using a Robot Operating System 2 (ROS 2) environment and stereo camera visualization. The contribution of this research is to present the development details and the proposed solution to solve issues encountered during the development. The development of script in the format of eXtensible Markup Language (XML), Unified Robot Description Format (URDF), and Simulation Description Format (SDF) are presented for describing a robot's physical structure, allowing a robotic system to be depicted in a tree structure, and defining the delta robot arm, which is made up of closed-loop kinematic chain linkage that will be simulated in Gazebo. For the results, se...

Abstract: This study presents the deposition of micro contact probe cell for IC testing deposited... more Abstract: This study presents the deposition of micro contact probe cell for IC testing deposited by dc sputtering technique on a glass substrate. Micro contact with thickness of 2800-7000 nm were deposited from Copper target at sputtering power of 125 W in argon ambient at a room temperature on a base layer of copper using mask. Then, the micro contacts were investigated by using profilometer. All the obtained results show the potential viability of the novel test fixture and thus solve the limitation of the pogo pin based testing tools by replacing them with the novel IC test fixture as demonstrated in this study.

Materials Science in Semiconductor Processing, 2021

Abstract This paper reports on the first investigation of the characteristics of 3D structures fo... more Abstract This paper reports on the first investigation of the characteristics of 3D structures formed in silicon carbide for the realisation of ultra-high performance nanoscale transistors, based on the FINFET topology. Capacitance–voltage characteristics show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices. Two distinct peaks in the conductance–voltage characteristics are observed, centred at the flatband voltages, where the amplitude of the high voltage peak correlates with the sidewall area. This suggests that the chemical behaviour of the sidewalls differ from those of the (0001) wafer surface. The breakdown electric field of the dielectric film grown on the 3D structure is in excess of 3 MV cm−1. It is demonstrated that 3D transistors (FINFETs) do not utilise the gate voltage range where the abnormal characteristics exist and so this work reports for the first time the possibility of high performance nanoscale transistors in silicon carbide that can operate at high temperatures.

Silicon carbide technology has made a significant improvements in these recent years, with a rang... more Silicon carbide technology has made a significant improvements in these recent years, with a range of different devices, such as diodes, junction field effect transistors (JFETs) and metaloxide-semiconductor field effect transistors (MOSFETs) becoming commercially viable. The availability of relatively large and high quality wafers of 4H-SiC for device development has facilitated exciting breakthroughs throughout the world. The application areas of 4H-SiC devices include extreme environments such as high power, high frequency, high temperatures as well as optoelectronics. SiC technology has became indispensable due to the increasing demands from industrial sectors including automotive, military and aerospace. One of the crucial challenges for 4H-SiC MOSFETs is to increase the channel mobility which is plagued by the high density of interface traps. Post oxidation annealing (POA) in nitrogen gas environment or nitridation has become a standard process for the fabrication of MOSFETs with acceptable channel mobility around 35 cm 2 /Vs, only about 4 % of the bulk mobility. POA using phosphoryl chloride (POCl 3) or phosphorus pentoxide (P 2 O 5) sources converts SiO 2 into phospho-silicate glass (PSG) and has succesfully improved the channel mobility by a factor of 3 in comparison to nitridation. However, PSG is a polar material that increases the instability of MOS devices characteristic especially at high temperatures. In this work, the effect of inclusion of phosphorus (at an atomic concentration below 1 %) on the high temperature characteristics (up to 300 • C) of the SiO 2 /SiC interface is investigated. Capacitance-voltage measurements taken over a range of frequencies have been utilized to extract parameters including flatband voltage, threshold voltage, effective oxide charge, and interface state density. The variation of these parameters with temperature has been investigated for bias sweeps in opposing directions and a comparison made between phosphorus doped and undoped oxides. At room temperature, the effective oxide charge for SiO 2 may be reduced by the phosphorus termination of dangling bonds at the interface. However, at high temperatures, the effective charge in the phosphorus doped oxide remains unstable and effects such as flatband voltage shift and threshold voltage shift dominate the characteristics. The instability in these characteristics was found to result from the trapped charges in the oxide (±10 12 cm −3) or near interface traps at the interface of the gate oxide and the semiconductor (10 12 to 10 13 cm −2 eV −1). Hence, the performance enhancements observed for phosphorus doped oxides are not realised in devices operated at elevated temperatures. v abnormal characteristics exist and so this work reports for the first time the possibility of high performance nanoscale transistors in silicon carbide that can operate at high temperatures. vi

Crystal Research and Technology, 2018

Pore wall thinning of mesoporous 4H-SiC by sacrificial oxidation has been performed. The dimensio... more Pore wall thinning of mesoporous 4H-SiC by sacrificial oxidation has been performed. The dimensions within the as-etched porous SiC are reduced during dry oxidation at 1100 • C by consuming SiC and removing the grown SiO2 in the subsequent HF dip step. The process reduces the average pore wall thickness from 27 nm to approximately 16 nm and reduces the thickness standard deviation from ±5 nm to ±1.4 nm for the investigated 9 hour oxidation interval. The new pore wall thinning method will enable controlled nanoscale size reduction capability for mesoporous 4H-SiC derived nanostructures.

Journal of Physics D: Applied Physics, 2019

The effect of phosphorus inclusion on different bias stress at high electric field on phosphorus ... more The effect of phosphorus inclusion on different bias stress at high electric field on phosphorus doped SiO 2 is investigated by electrical measurements of SiC MOS capacitors. 1 MHz C − V measurements with (1) different bias hold time (up to 999 s at room and high temperature of 250 • C), (2) different applied gate voltage (± 10, 20 and 30 V without stress time) and (3) different bias hold time at high voltage (± 30 V) were taken to observe the evolution of flatband voltage, effective oxide charge density and interface state density. In this investigation, the characteristics were measured in both sweep directions and compared to those obtained from undoped SiO 2 samples. At 250 • C, the flatband voltage of phosphorus-doped SiO 2 samples shows a significant shift to the positive with increasing bias hold time. Similar trends are observed with the characteristics obtained at room temperature, but the shifts are less significant. Both undoped and phosphorus-doped samples show positive flatband shift when a higher bias was applied for longer hold times, but the latter demonstrated more significant changes. We conclude that the phosphorus ions increase the instability of the electrical characteristics related to the generation of mobile charges in the SiO 2 , resulting in the injection of electrons from the semiconductor to the oxide. Therefore, the accumulated negative charge in phosphorus-doped SiO 2 resulting from the injection of electrons, which is enhanced by the mobile charge, is responsible for the enhanced positive shift in C − V and I − V characteristics.

Semiconductor Science and Technology, 2017

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The uniq... more A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300°C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO 2 /4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2,000 hours at 300°C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1,000 hours at 300°C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realize sensor interface circuits capable of operating above 300°C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

IOSR Journal of Engineering, 2013

This paper presents the effect of source voltage on performance of proposed Schmitt Trigger circu... more This paper presents the effect of source voltage on performance of proposed Schmitt Trigger circuit. The proposed circuit was designed based on Conventional Schmitt Trigger by manipulating the arrangement of transistors and the width-length ratio. The simulation results have been carried out based on Mentor Graphics software in term of propagation delay. The circuit layout has been designed and checked by using design rule check (DRC) and layout versus schematic (LVS) method. From these results, the proposed full swing CMOS Schmitt Trigger was able to operate at low voltage (0.8V-1.5V

Journal of Applied Physics, 2016

In this paper, the effect of inclusion of phosphorous (at a concentration below 1%) on the high t... more In this paper, the effect of inclusion of phosphorous (at a concentration below 1%) on the high temperature characteristics (up to 300 C) of the SiO 2 /SiC interface is investigated. Capacitance-voltage measurements taken for a range of frequencies have been utilized to extract parameters including flatband voltage, threshold voltage, effective oxide charge, and interface state density. The variation of these parameters with temperature has been investigated for bias sweeps in opposing directions and a comparison made between phosphorous doped and as-grown oxides. At room temperature, the effective oxide charge for SiO 2 may be reduced by the phosphorous termination of dangling bonds at the interface. However, at high temperatures, the effective charge in the phosphorous doped oxide remains unstable and effects such as flatband voltage shift and threshold voltage shift dominate the characteristics. The instability in these characteristics was found to result from the trapped charges in the oxide (610 12 cm À3) or near interface traps at the interface of the gate oxide and the semiconductor (10 12-10 13 cm À2 eV À1). Hence, the performance enhancements observed for phosphorous doped oxides are not realised in devices operated at elevated temperatures.

Research Journal of Applied Sciences, Engineering and Technology, 2014

A new optoelectronic device based on excitonpolariton was studied. In particular a Mach-Zehnder i... more A new optoelectronic device based on excitonpolariton was studied. In particular a Mach-Zehnder interference device fabricated by using a GaAs quantum well was studied. We simulated the output characteristics of Mach-Zehnder interference device by using a Finite Difference Time Domain (FDTD) method. Then we compared them with the experimental results measured in a low-temperature. After that we obtained the numerical values of electro-optic effect coefficients. Those were as large as 105×10-11 m/V for 4.5 K, while 74×10-11 m/V for 77 K. Therefore this estimation is considerably large, showing 57 (4 K) and 41 (77 K) times larger than conventional KDP crystal. This effect is probably caused by the excitonpolariton effect. Furthermore, we performed a photocurrent experiment to understand the transmitted light phase change characteristics, causing such large electro-optics effect at a comparatively higher temperature. Temperature dependence of photocurrent showed that the absorption edge and exciton peak remained constant up to 77 K, and then shifted to lower energy as the temperature increased. This probably explains how the large electro-optic effect can be obtained at a comparatively high temperature, i.e., 77 K.

Research Journal of Applied Sciences, Engineering and Technology, 2015

This study presents the fabrication process and analysis of micro contact probe cell for IC testi... more This study presents the fabrication process and analysis of micro contact probe cell for IC testing deposited by dc sputtering technique on a glass substrate. It is designed to solve and replace pogo pins in IC testing process. In previous study, the new model of test socket with new materials in different shapes were designed by using ANSYS as Finite Element Analysis (FEA) software and the best parameter were obtained. According to the optimized parameters, prototype structures of the micro-contacts are fabricated using DC Sputtering with materials like copper and tungsten on base copper on glass substrates. Micro contact with thickness of 2800-7000 nm were successively deposited on glass substrate at sputtering power of 125 W in argon ambient gas with pressure of 10-15×10-3 Torr at a room temperature. The structural and electrical properties of micro contact were investigated by using profilometer, Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) and four point probes. Results show that the film thickness increased as the deposition the time getting longer. The Root Mean Square (RMS) roughnesses obtained are all in a good quality. On the other hand, the resistivity of micro contacts was less than 4 uΩ-cm, which has good conductive properties. Consequently, this design is appropriate for replacing the conventional pogo pin based testing tools.

Przeglad Elektrotechniczny

Variable gain amplifier (VGA) is the key element for amplifying process in analog to digital conv... more Variable gain amplifier (VGA) is the key element for amplifying process in analog to digital converter (ADC). In this paper, a low voltage and wide bandwidth class AB VGA is designed using CEDEC 0.18-μm CMOS process for high speed applications. The result show that, the designed VGA has a wide bandwidth of 100-MHz and consumes power less than 125uW at 1V supply voltage. From the results it is also evident that the circuit is capable of working with high linearity and wide bandwidth. The frequency response (Gain) and the wide bandwidth of this class AB VGA is better than previously reported class AB VGA. Smaller transistors are used to make the chip small and it occupies only 0.003 µm 2 . Such a VGA is suitable for high-performance RF devices. Streszczenie. W artykule opisano niskonapięciowy, szerokopasmowy wzmacniacz klasy AB typu VGA (variable gain amplifier – wzmacniacz o zmiennym wzmocnieniu). Wzmacniacz zaprojektowano wykorzystując proces 0.18 um CMOS. Wykonano wzmacniacz o pasm...