navid khoshavi - Academia.edu (original) (raw)

Papers by navid khoshavi

Microelectronics Journal, 2015

Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technol... more Quantum-dot cellular automata (QCA) has been studied extensively as a promising switching technology at nanoscale level. Despite several potential advantages of QCA-based designs over conventional CMOS logic, some deposition defects are probable to occur in QCA-based systems which have necessitated fault-tolerant structures. Whereas binary adders are among the most frequently-used components in digital systems, this work targets designing a highly-optimized robust full adder in a QCA framework. Results demonstrate the superiority of the proposed full adder in terms of latency, complexity and area with respect to previous full adder designs. Further, the functionality and the defect tolerance of the proposed full adder in the presence of QCA deposition faults are studied. The functionality and correctness of our design is confirmed using high-level synthesis, which is followed by delineating its normal and faulty behavior using a Probabilistic Transfer Matrix (PTM) method. The related waveforms which verify the robustness of the proposed designs are discussed via generation using the QCADesigner simulation tool.

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014

Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation... more Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, Powergating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping.

International Symposium on Industrial Embedded Systems, 2011

This paper presents a software-based technique to detect control-flow errors using basic level co... more This paper presents a software-based technique to detect control-flow errors using basic level control-flow checking and inherent redundancy in commodity multi-core processors. The proposed detection technique is composed of two phases of basic and program-level control-flow checking. Basic-level control-flow error detection is achieved through inserting additional instructions into program at design time regarding to control-flow graph. Previous research shows that modern superscalar microprocessors already contain significant amounts of redundancy. Program-level control-flow checking can detect CFEs by leveraging existing microprocessors redundancy. Therefore, the cost of adding extra redundancy for fault tolerance is eliminated. In order to evaluate the proposed technique, three workloads quick sort, matrix multiplication and linked list utilized to run on a multi-core processor, and a total of 6000 transient faults have been injected on the processor. The advantage of the proposed technique in terms of performance and memory overheads and detection capability compared with conventional control-flow error detection techniques.

International On-Line Testing Symposium, 2011

This paper presents a software-based technique to recover control-flow errors using inherent redu... more This paper presents a software-based technique to recover control-flow errors using inherent redundancy in commodity multi-core processors. The proposed recovery technique is composed of two phases of control-flow error detection and control-flow error recovery. Previous research shows that modern superscalar microprocessors already contain significant amounts of redundancy. CFEs can be tolerated by leveraging existing microprocessors redundancy. Therefore, the cost of adding extra redundancy for fault tolerance is eliminated.

Euromicro Symposium on Digital Systems Design, 2011

This paper presents a software-based error detection technique through monitoring flow of the pro... more This paper presents a software-based error detection technique through monitoring flow of the programs in multithreaded architectures. This technique is based on the analysis of two key ideas: 1) Modifying the structure of traditional controlflow graphs used by control-flow checking methods so that they can be applied on multi-core and multi-threaded architectures. These achievements in designing control-flow error detectors lead to increase their applicability in current architectures. 2) Adjusting the locations of additional checking assertions in a given program in order to increase the ability of detecting possible control-flow errors along with significant reduction in overheads. The experimental results, through taking into account both detection coverage and overheads, demonstrate that on average about 94% of the control-flow errors can be detected by the proposed technique, more efficient compared to previous works.

2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing, 2010

This paper proposes two efficient software techniques, Control-flow and Data Errors Correction us... more This paper proposes two efficient software techniques, Control-flow and Data Errors Correction using Data-flow Graph Consideration (CDCC) and Miniaturized Check-Pointing (MCP), to detect and correct control-flow errors. These techniques have been implemented based on addition of redundant codes in a given program. The creativity applied in the methods for online detection and correction of the control-flow errors is using data-flow graph alongside of using control-flow graph. These techniques can detect most of the control-flow errors in the program firstly, and next can correct them, automatically. Therefore, both errors in the control-flow and program data which is caused by control-flow errors can be corrected, efficiently. In order to evaluate the proposed techniques, a post compiler is used, so that the techniques can be applied to every 80X86 binaries, transparently. Three benchmarks quick sort, matrix multiplication and linked list are used, and a total of 5000 transient faults are injected on several executable points in each program. The experimental results demonstrate that at least 93% and 89% of the control-flow errors can be detected and corrected without any data error generation by the CDCC and MCP, respectively. Moreover, the strength of these techniques is significant reduction in the performance and memory overheads in compare to traditional methods, for as much as remarkable correction abilities.

2010 15th CSI International Symposium on Computer Architecture and Digital Systems, 2010

This paper presents an efficient software technique to detect and correct control-flow and data e... more This paper presents an efficient software technique to detect and correct control-flow and data errors through addition of redundant codes in a given program. This technique is performed using both control-flow and data-flow graphs. Based on this method, most of control-flow errors in the program are, first detected, and next corrected automatically, so that not only errors in the control flow are detected / corrected but also, errors in the data of program because of control flow errors are repaired. In order to evaluate this technique, we use a simulator which can simulate an assembly code on the 80X86 microprocessors. We use three benchmarks: quick sort, matrix multiplication and linked list, and 1000 transient faults were injected on several executable points in the program code. The experimental results demonstrate that on average 93.5% of control flow errors are detected and corrected by CCDA automatically without any data error generation. It also shows that the performance and memory overheads of CCDA are noticeably less than previous related works.

2011 International Symposium on Electronic System Design, 2011

In this paper, a software behavior-based technique is presented to detect control-flow error. The... more In this paper, a software behavior-based technique is presented to detect control-flow error. The analysis of a key point leads to introduce the proposed technique: effective reduction of the overheads of control-flow checking statements through finding the best sequence of signatures for assigning to consecutive basic-blocks. To evaluate the proposed technique, a functional full-system simulator is used, and several well-known benchmarks are implemented on a quad-core shared memory processor. The experimental results, with regarding to both detection coverage and overheads, demonstrate that on average about 94% of the controlflow errors can be detected by the proposed technique, more efficiently.

Microelectronics Reliability, 2012

In this paper, a software behaviour-based technique is presented to detect control-flow errors in... more In this paper, a software behaviour-based technique is presented to detect control-flow errors in multi-core architectures. The analysis of two key points leads to introduce the proposed technique: (i) employing under-utilized CPU resources in multi-core processors to check the execution flow of the programs in parallel with their executions to moderate the performance overhead of previous software-based techniques, and to enhance the applicability of them in current architectures. (ii) Adjusting the locations of additional statements in a given program in order to increase the ability of detecting possible control-flow errors along with significant reduction in overheads. To evaluate the proposed technique, a quad-core processor system is used as the simulation environment, and the behaviour of several well-known single-and multi-threaded benchmarks have been studied. The experimental results, regarding to both detection coverage and performance overhead, demonstrate that on average about 90% of the control-flow errors can be detected by the proposed technique with just about 10% performance overhead, compared to at least 30% imposed by the previous techniques.

International Conference on Microelectronics, 2012

In this paper we consider two software-based control-flow error recovery methods with a rollback ... more In this paper we consider two software-based control-flow error recovery methods with a rollback recovery mechanism for using in multithreaded architectures. Disregarding to thread interactions between different threads by previous CFE recovery techniques caused these methods not be suitable in multithreaded architectures. Furthermore, the high memory and performance overheads of these techniques may be problematic for real-time embedded systems which have tight memory and performance budget. Therefore, regarding to the importance of handling the CFE, unsuitability of the conventional related techniques to be utilized in the modern processors and high memory and performance overheads of previous CFE recovery techniques, two low-cost control-flow error recovery techniques, CFE Recovery using Data-flow graph Consideration (CRDC) and CFE Recovery using Macro block-level Check pointing (CRMC), are presented in this paper. The proposed recovery techniques are composed of two phases of control-flow error detection and control-flow error recovery. These phases are achieved through inserting additional instructions into program at compile time regarding to dependency graph. This graph is extracted to model control-flow and data dependencies among basic blocks and thread interactions between different threads of a program. In order to evaluate the proposed techniques, five multithreaded benchmarks Quick Sort, Matrix Multiplication, Bubble Sort, Linked List and Fast Fourier Transform utilized to run on a multi-core processor, and a total of 5000 transient faults has been injected into several executable points of each program. Fault injection experiments show that tolerable performance and memory overheads with noticeable error recovery coverage can be achieved via proposed techniques.