nouma izeboudjen - Academia.edu (original) (raw)

Papers by nouma izeboudjen

The electrocardiogram (ECG) is an important tool for providing information about functional statu... more The electrocardiogram (ECG) is an important tool for providing information about functional status of the heart. Analysis of ECG is of great importance in the detection of cardiac anomalies. This paper presents a diagnostic system for cardiac arrhythmias from ECG data, using an artificial neural network classifier. In this article we propose a new method for the detection of ventricular and supra ventricular tachycardia (VT and SVT) using probabilistic neural networks (PNN). After acquisition and pre-processing of ECG signals, we proceed to determine the relevant necessary parameters for the diagnostic; these are: the RR interval, the heart rate, the QRS duration and the QRS complex. To reduce the number of input data of the classifier we apply the discrete wavelet transform for the compression wave of QRS, therefore the total number of parameters applied to the input of our classifier are 13 parameters. The proposed approach is tested using the MIT-BIH database and the results were obtained with rate of classification of 62.5 % for VT and 85.30 % for SVT. The results provided in this article are promising for the development of an automated method for classifying cardiac arrhythmias.

Indonesian Journal of Electrical Engineering and Computer Science

Maximum power point tracking (MPPT) is a technique used in extracting the maximum power from a ph... more Maximum power point tracking (MPPT) is a technique used in extracting the maximum power from a photovoltaic panel (PV) under different weather conditions. The last decade has witnessed a wide variety of algorithm based on MPPT controllers, ranging from simple to more complexe ones. Each of them has its own advantage and disadvantage. Hence, it is crutial to propose methods that are both simple and effective to track and maintain the MPPT of a PV system, even under partial shading conditions. In this study, we propose a new bio inspired method namely seagull optimization algorithm (SOA) for solving the MPPT problem in a PV system. To evaluate the proposed SOA _MPPT performance in terms of accuracy, convergence and stability, a simulation methodology is used. First, by tunning the appropriate parameters, then, we consider the following scenarios: rapid change of solar irradiation, temperature, and three patterns to test partial shading effect. The results are compared with latest bio-...

Lecture notes in networks and systems, 2023

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

This paper describes a new reuse oriented design methodology for artificial neural networks (ANNs... more This paper describes a new reuse oriented design methodology for artificial neural networks (ANNs) implementation. The proposed approach is mainly based on a VHDL synthesis environment that uses a pre-designed hierarchical and parametric library suited for different ANN topologies. To validate this approach, a case study of the three-layer back-propagation algorithm is illustrated, A VHDL description of a (5-3-2) ANN circuit is passed through synthesis tool, GALILEO for FPGA implementation. The preliminary results are very successful, since the whole network has been implemented onto only one FPGA. It has a clock frequency of about 16 MHz and can be used in some real time applications

The System-on-Chip (SoC) refers to a mini computer independent system where all essential parts o... more The System-on-Chip (SoC) refers to a mini computer independent system where all essential parts of computing are integrated into a single FPGA or ASIC chip and where the application is executed by a program, which is loaded into an on chip memory or an off shelf component. However the increasing complexity of embedded systems and the staggering costs associated with designing systems-on-chip imposes system designer and companies to seek collaboration on a variety of intellectual property issues. Consequently the cost of building SoC is increasing significantly when the system integrates several parts. This paper presents Hardware/Software development of an embedded system on chip for network application, based on the Opencores and Opensources design concepts, in order to build an embedded systemon-chip for network applications at free cost. This approach is based on the IP (Intellectual Property) reuse strategy which facilitates the rapid creation and verification design process. In this paper we define the methodology adopted to construct our SoC. The system includes a hardware part and a software part which are linked to each other through a µClinux operating system. For the hardware part, an HDL file describing all the cores of the library is created. The SoC architecture is mapped into the virtex5 XC5VLX50-1FF676 FPGA development board. Results show that the SoC architecture occupies 27% of logic resources and 35% of IOBs (In/Out Blocs). The software development of the embedded network application includes two parts: Configuration and compilation of the µClinux and programming of network application. In this part we have chosen an embedded network TFTP (trivial file transfer protocol) client as a test application. The results of the software part shows that the boot of µClinux and TFTP client test under the Or1ksim which is an instruction set simulator as well as the frame transfers were successfully done.

2021 International Conference on Information Systems and Advanced Technologies (ICISAT), 2021

This paper deals with the Hardware/Software development of a forest fires prediction system. To a... more This paper deals with the Hardware/Software development of a forest fires prediction system. To automate the forest fires prediction process, we propose a machine learning algorithm based prediction model that allows the prediction and detection in intelligent way. The software part is related to the forest fires prediction application that is built using the decision tree algorithm as a forest fires classifier and fire occurrences predictor. The hardware part of the proposed system is represented by the MicroBlaze based architecture that includes the MicroBlaze processor and a number of basic peripherals for the forest fires prediction functionality test and validation. The embedded system constitutes the processing part of a sensor node that process data and takes decision at sensor node level; hence there is no need for sending the data to the base station for decision. The whole architecture is mapped to the Artix7 FPGA and prototyped using the Nexys4 DDR board. The on-chip verification shows the validation of the proposed FPGA-based intelligent forest fires prediction system.

Today, with the explosion of the IP network protocol, communication traffic is mainly dominated b... more Today, with the explosion of the IP network protocol, communication traffic is mainly dominated by data traffic, unlike in the past it was dominated by telephony driven voice. This phenomenon has lead to the emergence of voice over data (VOIP) equipment that can carry voice, data and also video on a single network. The idea behind VOIP is to use the IP

The aim of this paper is to present a new System on Chip (SoC) reconfigurable gateway architectur... more The aim of this paper is to present a new System on Chip (SoC) reconfigurable gateway architecture for Voice over Internet Telephony (VOIP). Our motivation behind this work is justified by the following arguments: most of VOIP solutions proposed in the market are based on the use of a general purpose processor and a DSP circuit. In these solutions, the use of the serial multiply accumulate circuit is very limiting for the signal processing. Also, in embedded VOIP based DSP applications, the DSP works without MMU (memory management unit). This is a serious limitation because VOIP solutions are multi-task based. In order to overcome these problems, we propose a new VOIP gateway architecture built around the OpenRisc-1200-V3 processor. This last one integrates a DSP circuit as well as a MMU. The hardware architecture is mapped into the VIRTEX-5 FPGA device. We propose a design methodology based on the design for reuse and design with reuse concepts. We demonstrate that the proposed SoC...

2020 International Conference on Electrical Engineering (ICEE), 2020

We expose in this work, the decision tree based intellectual property (IP) core development for f... more We expose in this work, the decision tree based intellectual property (IP) core development for forest fires prediction. We introduce its integration into the MicroBlaze based SoC architecture that constitutes the processing part of the sensor node. The aim is to speed up the predicting process by giving the decision locally at sensor node level. The decision tree based predictive model is simulated and trained using MATLAB tool for the tree generation; prior to its hardware development using the high level synthesis approach. The performance of the decision tree classifier in terms of accuracy and recall are about 75% and 0.88, respectively. The hardware implementation results of the decision tree based forest fires prediction system on chip show that the developed IP core requires few resources.

The embedded SoC (System on Chip) solution aims to realise portable systems, while reducing power... more The embedded SoC (System on Chip) solution aims to realise portable systems, while reducing power dissipation, chip interconnects and device size. However the increasing complexity of embedded systems and the staggering costs associated with designing systems-on-chip imposes system designer and companies to seek collaboration on a variety of intellectual property issues. Consequently the cost of building SoC is increasing significantly when the system integrates several parts. This paper aims to exploit the advantage of a new approach and design method based on Opencores and Opensources design concepts in order to build in an embedded system on chip for network applications at free cost. This approach is based in the IP (Intellectual Property) reuse strategy facilitates the rapid creation and verification design process. In this paper we define the methodology adopted to construct the open SoC. The designed platform aims to provide a rapid prototype design for system on chip. The sy...

ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers... more ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm2. Regarding the power consumption, RTL power estimation is given.

Forest fire is a disaster that causes economic and ecological damage and human life threat. Thus ... more Forest fire is a disaster that causes economic and ecological damage and human life threat. Thus predicting such critical environmental issue is essential to mitigate this threat. In this paper we propose a decision tree based system for forest fire prediction. The aim being the integration of the decision tree classifier as a part of the smart sensor node architecture that allows fire prediction in automated and intelligent way without requiring human intervention. The fire prediction is based on the meteorological data corresponding to the critical weather elements that influence the forest fire occurrence, namely temperature, relative humidity and wind speed. We have obtained accuracy about 82.92% regarding the software implementation of the proposed DT based forest fire prediction system.

The IP (Intellectual Property) cores from Opencores are portable building blocks described at RTL... more The IP (Intellectual Property) cores from Opencores are portable building blocks described at RTL level; most available components are wishbone bus compatible. These IP cores have been used in numerous SoC architectures. The benefits of using these IPs are flexibility, reusability and also reduction of the whole design cost owing to the accessibility of these IP cores for free. However these IPs are not designed with low power saving features, which is an important issue in SoC design. In this paper, we propose a low power strategy for wishbone compatible IPs based SoC design using an IP level clock gating. The aim is to reduce power in the whole SoC based on these IPs, designed with low power saving features. Primary results show that the proposed scheme at IP level achieves dynamic power reduction, ranging from 31 % to 66.4%.

A new neural network system for classification of the cardiac rhythm is presented in this paper. ... more A new neural network system for classification of the cardiac rhythm is presented in this paper. The system is composed of two neural network classifiers : a morphological classifier cascaded to a timing classifier. While the morphological classifier classify the P and QRS complexes into normal and/or abnormal beats, the timing classifier takes as inputs the information of the morphological classifier and the duration of the PP, PR and RR intervals and output the following arrhythmias: sinus tachycardia, sinus bradycardia, sinus arrhythmia, atrial extrasystoles, atrial tachycardia, atrial fibrillation, atrial flutter, ventricular tachycardia, ventricular extrasystoles, ventricular flutter and supraventricular tachycardia in addition to the normal sinus rhythm.

2015 4th International Conference on Electrical Engineering (ICEE), 2015

Proceedings of the 4th International Conference on Circuits Systems and Signals, Jul 22, 2010

Nc, 1998

Nowadays support systems for diagnosis constitute technical means which are necessary in the medi... more Nowadays support systems for diagnosis constitute technical means which are necessary in the medical field, particularly in cardiology. In such field, traditional methods of classification such as the tree approach and the statistical one are inadequate. The introduction of emerging smart technologies such as neural networks is more efficient than other methods. The neural network approach is proved as an effective technique for solving the classification problem. The aim of this paper is to design a neural network classifier, able to reliably identify cases of pathological tachycardia family such as ventricular tachycardia (SVT) and supra ventricular tachycardia (SVT). To achieve this goal, we use several neuronal network algorithms namely the multilayer perceptron network (MLP), the Kohonen Self-Organizing Maps (SOM), the learning vector quantization (LVQ) and the probabilistic neural network (PNN). Test of performances are conducted to verify the reliability margin proposed neura...