ramzi jaber - Academia.edu (original) (raw)
Papers by ramzi jaber
Cornell University - arXiv, Nov 8, 2022
Recently, the demand for portable electronics and embedded systems has increased. These devices n... more Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this thesis proposes novel ternary circuits aiming to reduce the energy (Power Delay Product (PDP)) to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units (TALU). The ternary logic gates are seven unary operators of the ternary system (A 1 , A 2 ,Ā 2 , A 1 , 1.Ā n , 1.Ā p , and the Standard Ternary Inverter (STI)Ā), and Ternary NAND based on Carbon Nanotube Field-Effect Transistor (CNFET). Ternary combinational circuits, two different designs for Ternary Decoders (TDecoder) and Ternary Multiplexer (TMUX): (1) TDecoder1 using CNFET-based proposed unary operators and TDecoder2 using Double-Pass Logic (DPL) binary gates. (2) TMUX using CNFET-based proposed unary operators. And Ternary Arithmetic Logic Units are three different designs for Ternary Half-Adders (THA) and Ternary Multipliers (TMUL): (1) The first design uses the proposed TDecoder1, STI, and TNAND. (2) While the second design uses the cascading proposed TMUX. (3) As for the third design, it uses the proposed unary operators and TMUX. This thesis applies the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2) to achieve its objective. The proposed designs are compared to the latest ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. Simulations are performed to prove the efficiency of the proposed designs. The results demonstrate the advantage of the proposed designs with a reduction over 73% in terms of transistors count for the THA and over 88%, v 99%, 98%, 84%, 98%, and 99% in energy consumption for the STI, TNAND, TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curve (NIC) and Monte Carlo analysis for major process variations (TOX, CNT Diameter, CNT's Count, and Channel length) were studied. The results confirmed that the third proposed THA3 and TMUL3 had higher strength and higher noise tolerance, among other designs. In addition, the second objective is using ternary data transmission to improve data communications between computer hosts. Also, this thesis proposes a bi-directional circuit that contains two converters: (1) A binary-to-ternary converter and (2) a ternary-to-binary converter. Finally, logical analysis and simulation results prove the merits of the approaches compared to existing designs in terms of transistor count, reduced latency, and energy efficiency. vi Contents Contents vii List of Tables xi List of Figures xiv Abbreviations xvii Symbols xix Appendix B CNFET-Based Designs of Ternary Half-Adder using a Novel "Decoderless" Ternary Multiplexer based on Unary Operators
Ramzi Ali Jaber, Aug 19, 2020
IEEE Access, 2021
The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread ve... more The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most of them depend on batteries to operate. The target of this work is to decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding energy consumption over binary circuits and (2) using carbon nanotube field-effect transistors (CNFET) that show better performance than CMOS. This work proposes ternary combinational circuits using 32 nm CNFET: Ternary Half Adder (THA) with 36 transistors and Ternary Multiplier (TMUL) with 23 transistors. To reduce energy consumption by utilizing the unary operator of the ternary system and employing two voltage supplies (<inline-formula> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula>/2). The result of extensive HS...
2020 32nd International Conference on Microelectronics (ICM), 2020
Multiple-valued logic (MVL) circuit has many-valued logic in each digit to lower interconnections... more Multiple-valued logic (MVL) circuit has many-valued logic in each digit to lower interconnections and energy consumption over a binary logic circuit. Therefore, this paper proposes a ternary multiplier (TMUL) that reduce energy consumption in the context of low-power embedded circuits. The CNTFET-based TMUL circuit use only cascading proposed ternary multiplexer to reduce the transistors count and improve performance efficiency. Extensive simulations along with several benchmark designs using HSPICE, prove the merits of the proposed TMUL by reducing energy consumption, improving the noise tolerance, and robustness to process variations (TOX, Channel length, CNT Count, and CNT Diameter).
2020 International Conference on Innovation and Intelligence for Informatics, Computing and Technologies (3ICT), 2020
Energy consumption is a critical factor to be reduced when designing embedded systems and IoT dev... more Energy consumption is a critical factor to be reduced when designing embedded systems and IoT devices. By using Multiple-valued logic (MVL) circuits, interconnections complexity and energy consumption are decreased in comparison to binary systems. This paper uses MVL circuits to present a ternary half-adder (THA) with reduced energy consumption to maintain the battery usage in nano-scale embedded systems and IoT devices. The proposed CNTFET-based circuit uses a dualvoltage (Vdd and Vdd/2) and novel unary operators to improve the performance. Extensive HSPICE simulations show impressive improvements in reducing transistors count, decreasing energy consumption, increasing noise tolerance, and enhancing the robustness of process variations compared to previous circuits.
2021 International Conference on Innovation and Intelligence for Informatics, Computing, and Technologies (3ICT), 2021
This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using TMUXs... more This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using TMUXs (Ternary Multiplexers) and unary operators. The target of the proposed designs is to minimize energy consumption in nanoscale embedded circuits to improve their battery usage. To achieve that, different techniques are used: 32-nm CNTFET tranisistor, Multiple-Valued Logic (MVL), two voltage supplies (Vdd,Vdd/2)(V_{dd},\ V_{dd}/2)(Vdd,Vdd/2) TMUXs, and unary operators to reduce the transistors' number and PDP (Power Delay Product). Extensive simulations using HSPICE for different Process, Voltage, Temperature (PVT), and noise effects are applied. The obtained results show improvements regarding PDP, robustness of process variations, and noise tolerance with respect to recent similar designs.
2020 32nd International Conference on Microelectronics (ICM), 2020
The limitations in binary data transmission are mainly for low speed and a notable increase in en... more The limitations in binary data transmission are mainly for low speed and a notable increase in energy consumption. Whereas, Multiple-Valued Logic (MVL) has over two-valued logic to increase the speed and to reduce energy consumption. Therefore, this paper proposes a Ternary-to-Binary Converter based on Carbon Nano-Tube Field Effect Transistors (CNFETs) to be used in ternary data transmission. The proposed converter has two ternary trits as input and four binary bits as output. Logical analysis and simulation results, using the HSPICE simulator, prove the merits of the implementation compared to existing designs regarding the transistors count, propagation delay, and energy consumption.
IEEE Access, 2021
Multiple-Valued Logic systems present significant improvements in terms of energy consumption ove... more Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works. INDEX TERMS Carbon nano-tube field effect transistors (CNTFET), Noise immunity curve (NIC), PVT variations, ternary logic circuits, unary operators.
2019 31st International Conference on Microelectronics (ICM), 2019
The ternary circuit has an advantage over the binary circuit concerning interconnect complexity, ... more The ternary circuit has an advantage over the binary circuit concerning interconnect complexity, propagation delay, and energy consumption. This paper proposes a novel binary-to-ternary converter using Double Pass-Transistor (DPL) with four bits as input and three trits as output. The importance of this work is gained through its potential to increase the data rate, and reduce power consumption. Also, the proposed converter can be used as a bridge between binary and ternary circuits. The proposed circuit is simulated and tested using the Micro-Cap V10 PSPICE simulator with CMOS process technology. It is then compared to different binary-to-ternary converters to conclude that significant improvement achieved.
2018 International Arab Conference on Information Technology (ACIT), 2018
This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) ... more This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) Binary logic gates, in digital CMOS technology. The physical design of the circuits is simulated and tested with Micro-Cap 10 SPICE simulator. The Proposed Ternary Decoder circuit can be used in VLSI design. The Proposed decoder circuit will be the basic circuit to create other Ternary Logic Circuits like Ternary Logic Gates, Ternary Memory, Adder, Multiplier, Multiplexer, and others. The simulation results demonstrate the merits of the approach in terms of reduced number of transistors by 25% compared to the existing ternary decoder.
IEEE Access
Recently, the demand for portable electronics and embedded systems has increased. These devices n... more Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [Standard Ternary Inverter (ST I), Ternary NAND (T N AN D)] and combinational circuits [Ternary Decoder (T Decoder), Ternary Half-Adder (T HA), and Ternary Multiplier (T M U L)] using Carbon Nano-Tube Field Effect Transistors (CNFET). The paper employs the best tradeoff between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2). The five proposed designs are compared to the latest fifteen ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. One hundred eighty simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the ST I, T N AN D, T Decoder, T HA, and T M U L respectively.
2012 2nd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA), 2012
Cornell University - arXiv, Nov 8, 2022
Recently, the demand for portable electronics and embedded systems has increased. These devices n... more Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this thesis proposes novel ternary circuits aiming to reduce the energy (Power Delay Product (PDP)) to preserve battery consumption. The proposed designs include eight ternary logic gates, three ternary combinational circuits, and six Ternary Arithmetic Logic Units (TALU). The ternary logic gates are seven unary operators of the ternary system (A 1 , A 2 ,Ā 2 , A 1 , 1.Ā n , 1.Ā p , and the Standard Ternary Inverter (STI)Ā), and Ternary NAND based on Carbon Nanotube Field-Effect Transistor (CNFET). Ternary combinational circuits, two different designs for Ternary Decoders (TDecoder) and Ternary Multiplexer (TMUX): (1) TDecoder1 using CNFET-based proposed unary operators and TDecoder2 using Double-Pass Logic (DPL) binary gates. (2) TMUX using CNFET-based proposed unary operators. And Ternary Arithmetic Logic Units are three different designs for Ternary Half-Adders (THA) and Ternary Multipliers (TMUL): (1) The first design uses the proposed TDecoder1, STI, and TNAND. (2) While the second design uses the cascading proposed TMUX. (3) As for the third design, it uses the proposed unary operators and TMUX. This thesis applies the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2) to achieve its objective. The proposed designs are compared to the latest ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. Simulations are performed to prove the efficiency of the proposed designs. The results demonstrate the advantage of the proposed designs with a reduction over 73% in terms of transistors count for the THA and over 88%, v 99%, 98%, 84%, 98%, and 99% in energy consumption for the STI, TNAND, TDecoder, TMUX, THA, and TMUL, respectively. Moreover, the noise immunity curve (NIC) and Monte Carlo analysis for major process variations (TOX, CNT Diameter, CNT's Count, and Channel length) were studied. The results confirmed that the third proposed THA3 and TMUL3 had higher strength and higher noise tolerance, among other designs. In addition, the second objective is using ternary data transmission to improve data communications between computer hosts. Also, this thesis proposes a bi-directional circuit that contains two converters: (1) A binary-to-ternary converter and (2) a ternary-to-binary converter. Finally, logical analysis and simulation results prove the merits of the approaches compared to existing designs in terms of transistor count, reduced latency, and energy efficiency. vi Contents Contents vii List of Tables xi List of Figures xiv Abbreviations xvii Symbols xix Appendix B CNFET-Based Designs of Ternary Half-Adder using a Novel "Decoderless" Ternary Multiplexer based on Unary Operators
Ramzi Ali Jaber, Aug 19, 2020
IEEE Access, 2021
The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread ve... more The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most of them depend on batteries to operate. The target of this work is to decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding energy consumption over binary circuits and (2) using carbon nanotube field-effect transistors (CNFET) that show better performance than CMOS. This work proposes ternary combinational circuits using 32 nm CNFET: Ternary Half Adder (THA) with 36 transistors and Ternary Multiplier (TMUL) with 23 transistors. To reduce energy consumption by utilizing the unary operator of the ternary system and employing two voltage supplies (<inline-formula> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula>/2). The result of extensive HS...
2020 32nd International Conference on Microelectronics (ICM), 2020
Multiple-valued logic (MVL) circuit has many-valued logic in each digit to lower interconnections... more Multiple-valued logic (MVL) circuit has many-valued logic in each digit to lower interconnections and energy consumption over a binary logic circuit. Therefore, this paper proposes a ternary multiplier (TMUL) that reduce energy consumption in the context of low-power embedded circuits. The CNTFET-based TMUL circuit use only cascading proposed ternary multiplexer to reduce the transistors count and improve performance efficiency. Extensive simulations along with several benchmark designs using HSPICE, prove the merits of the proposed TMUL by reducing energy consumption, improving the noise tolerance, and robustness to process variations (TOX, Channel length, CNT Count, and CNT Diameter).
2020 International Conference on Innovation and Intelligence for Informatics, Computing and Technologies (3ICT), 2020
Energy consumption is a critical factor to be reduced when designing embedded systems and IoT dev... more Energy consumption is a critical factor to be reduced when designing embedded systems and IoT devices. By using Multiple-valued logic (MVL) circuits, interconnections complexity and energy consumption are decreased in comparison to binary systems. This paper uses MVL circuits to present a ternary half-adder (THA) with reduced energy consumption to maintain the battery usage in nano-scale embedded systems and IoT devices. The proposed CNTFET-based circuit uses a dualvoltage (Vdd and Vdd/2) and novel unary operators to improve the performance. Extensive HSPICE simulations show impressive improvements in reducing transistors count, decreasing energy consumption, increasing noise tolerance, and enhancing the robustness of process variations compared to previous circuits.
2021 International Conference on Innovation and Intelligence for Informatics, Computing, and Technologies (3ICT), 2021
This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using TMUXs... more This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using TMUXs (Ternary Multiplexers) and unary operators. The target of the proposed designs is to minimize energy consumption in nanoscale embedded circuits to improve their battery usage. To achieve that, different techniques are used: 32-nm CNTFET tranisistor, Multiple-Valued Logic (MVL), two voltage supplies (Vdd,Vdd/2)(V_{dd},\ V_{dd}/2)(Vdd,Vdd/2) TMUXs, and unary operators to reduce the transistors' number and PDP (Power Delay Product). Extensive simulations using HSPICE for different Process, Voltage, Temperature (PVT), and noise effects are applied. The obtained results show improvements regarding PDP, robustness of process variations, and noise tolerance with respect to recent similar designs.
2020 32nd International Conference on Microelectronics (ICM), 2020
The limitations in binary data transmission are mainly for low speed and a notable increase in en... more The limitations in binary data transmission are mainly for low speed and a notable increase in energy consumption. Whereas, Multiple-Valued Logic (MVL) has over two-valued logic to increase the speed and to reduce energy consumption. Therefore, this paper proposes a Ternary-to-Binary Converter based on Carbon Nano-Tube Field Effect Transistors (CNFETs) to be used in ternary data transmission. The proposed converter has two ternary trits as input and four binary bits as output. Logical analysis and simulation results, using the HSPICE simulator, prove the merits of the implementation compared to existing designs regarding the transistors count, propagation delay, and energy consumption.
IEEE Access, 2021
Multiple-Valued Logic systems present significant improvements in terms of energy consumption ove... more Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works. INDEX TERMS Carbon nano-tube field effect transistors (CNTFET), Noise immunity curve (NIC), PVT variations, ternary logic circuits, unary operators.
2019 31st International Conference on Microelectronics (ICM), 2019
The ternary circuit has an advantage over the binary circuit concerning interconnect complexity, ... more The ternary circuit has an advantage over the binary circuit concerning interconnect complexity, propagation delay, and energy consumption. This paper proposes a novel binary-to-ternary converter using Double Pass-Transistor (DPL) with four bits as input and three trits as output. The importance of this work is gained through its potential to increase the data rate, and reduce power consumption. Also, the proposed converter can be used as a bridge between binary and ternary circuits. The proposed circuit is simulated and tested using the Micro-Cap V10 PSPICE simulator with CMOS process technology. It is then compared to different binary-to-ternary converters to conclude that significant improvement achieved.
2018 International Arab Conference on Information Technology (ACIT), 2018
This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) ... more This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) Binary logic gates, in digital CMOS technology. The physical design of the circuits is simulated and tested with Micro-Cap 10 SPICE simulator. The Proposed Ternary Decoder circuit can be used in VLSI design. The Proposed decoder circuit will be the basic circuit to create other Ternary Logic Circuits like Ternary Logic Gates, Ternary Memory, Adder, Multiplier, Multiplexer, and others. The simulation results demonstrate the merits of the approach in terms of reduced number of transistors by 25% compared to the existing ternary decoder.
IEEE Access
Recently, the demand for portable electronics and embedded systems has increased. These devices n... more Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, Multi-Valued Logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [Standard Ternary Inverter (ST I), Ternary NAND (T N AN D)] and combinational circuits [Ternary Decoder (T Decoder), Ternary Half-Adder (T HA), and Ternary Multiplier (T M U L)] using Carbon Nano-Tube Field Effect Transistors (CNFET). The paper employs the best tradeoff between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate and applying the dual supply voltages (Vdd, and Vdd/2). The five proposed designs are compared to the latest fifteen ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies. One hundred eighty simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the ST I, T N AN D, T Decoder, T HA, and T M U L respectively.
2012 2nd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA), 2012