rita jain - Academia.edu (original) (raw)
Papers by rita jain
2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2018
The world peace is disrupting day by day in today’s scenario, increase in terrorism has risen the... more The world peace is disrupting day by day in today’s scenario, increase in terrorism has risen the need of advanced armed technologies in today’s world, there’s no single country in world without dispute, and with disputes comes the riots, uncontrollable mobs, mass fire, bombings etc. This paper is aimed to research into military vehicle, which is capable enough to control a large mob of protesters using microwave beam named as "Heat Ray", which would produce heating sensation on target bodies when incident, and high frequency sound wave named as "Acoustic Gun", which will induce highly vibrating sound beam on the target body, creating a vibrating atmosphere around the target, resulting in nausea and intense headache. The vehicle is also able to diffuse and dispose bomb using a robotic limb with Electromagnetic Pulse (EMP) emitter, which would diffuse the circuit of the live bomb when incidented on it. By converting the constraint conditions of delivery and functions, the model proposed in the paper is not an actual human carrier, but is a manually controlled Unmanned Ground Vehicle (UGV) which is theoretically able to flea the uncontrollable mobs and dispose and diffuse bomb, which is shown in further study.
Abstract— the evolution of compact, light-weight, low-power, and high-quality displays has caus... more Abstract— the evolution of compact, light-weight, low-power, and high-quality displays has caused a large demand for liquid crystal display (LCD) drivers, with features such as low cost, low power dissipation, high speed, and high resolution. we propose a low-Quiescent current Two-Input/Output buffer with class A-B output stage for LCD driver applications. The propose buffer amplifier achieve high speed driving performance, draws a small quiescent current during static operation and offer a rail to rail communication-mode input rang Two-Input/Output buffer with class A-B output stage for LCD driver. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.2 µA static current is consumed in one channel driver. The settling time to settle within 0.15...
The advent of information and communication technologies (ICT), learning has entered into an era ... more The advent of information and communication technologies (ICT), learning has entered into an era of change unparalleled in this generation. The issue is, how theoretical knowledge can apply to real world problem? Academics worldwide have come to the conclusion that traditional learning methods must give way to Digital learning (D-learning). However, in order to change a paradigm, there must be a change in the way that people believe, think and act. A change to Digital learning in engineering education is a paradigm that has its associated challenges. Innovations are required so as to accomplish Digital learning in engineering education. Developing Digital learning tools that will take engineering education beyond traditional capabilities is a part of this challenge. In this paper, I have presented a review on design and development of virtual classroom environment using real-time streaming technology for live and online activity. Student can access the lecture even in presence of mo...
This paper presents design of CMOS voltage reference circuit, by replacing the analog amplifier i... more This paper presents design of CMOS voltage reference circuit, by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit with extended voltage range, and a digital control circuit with minimum supply voltage. The reference voltage circuits are used to adjust the clock frequency to regulate the charge pump to a steady output voltage under a large range of current loads. The parameters such as output resistances and power conversion efficiencies are the performance measures of charge pumps circuits. The propose circuits are design using transmission gate logic. Using transmission gate maximum voltage range is expected and no longer limited by the breakdown voltages of the devices.
Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calc... more Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calculations supported sixteen Sutras that are discovered by Sri Bharti Krishna Tirthaji. Any processor’s performance depends on 3 vital factors specifically speed, space and power. a higher trade-off between these factors makes the processor, a good one. Multipliers are the usually used architectures within the processor. If the performance of those multipliers is improved then powerful processors is created in future. during this paper, the planned number style supported the sutra‘Urdhva Tiryakbhyam’ of Vedic arithmetic is analyzed and also the performance results of the number are compared with standard multipliers. Extremely economical arithmetic operations are necessary to appreciate the specified performance in several period of time systems and digital image method applications. altogether these applications, one of the necessary arithmetic operations of performed is to multiply and a...
IP Annals of Prosthodontics and Restorative Dentistry, 2020
INTERNATIONAL JOURNAL OF COMMERCE AND BUSINESS MANAGEMENT, 2016
International Journal of Advanced Research in Computer Science and Electronics Engineering, Jan 28, 2013
Image and video compression is one of the major components used in video-telephony, videoconferen... more Image and video compression is one of the major components used in video-telephony, videoconferencing and multimedia-related applications where digital pixel information can comprise considerably large amounts of data. Management of such data can involve significant overhead in computational complexity and data processing. Compression allows efficient utilization of channel bandwidth and storage size. In this paper we describe the design and implementation of a fully pipelined architecture for implementing the JPEG image compression standard. The architecture exploits the principles of pipelining and parallelism in order to obtain high speed and throughput. The design was synthesized using Xilinx9.2i and Spartan 3 FPGAs, and simulation was carried out using ModelSim environment. It has been estimated that the entire architecture can be implemented on a single FPGA to yield a clock rate of about 100 MHz which allow an input rate of 24 bit input RBG.
Computing in Science & Engineering, 2014
These days most microprocessor and microcontroller designs are based on Reduced Instruction Set C... more These days most microprocessor and microcontroller designs are based on Reduced Instruction Set Computer (RISC) core and many operation such as Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system. This paper represent the design of a Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) system described using VHDL and implement in a Field Programmable Logic Array (FPGA). This RISC is a 20 bit processor.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)
The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation ... more The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation of their quantum cost, gate count, garbage outputs and depth of the circuit. The simulation results are obtain edinXilinxISE version 14.1. Reversible logic circuits are designed and implemented using Verilog code. The circuit is beneficial for further designing of reversible digital designs with low power loss. The devices designed through this circuit are expected to have a better performance as compared to the existing circuits.
In this paper, the VHDL design and implementation of BPSK, BASK and BFSK modulator and demodulato... more In this paper, the VHDL design and implementation of BPSK, BASK and BFSK modulator and demodulator with mixed domain performance analysis under different software are presented. The modulators are widely used in communication system either wired or wireless also the applications of these devices are ranging from personal to industrial. Because the every techniques has their own advantages and disadvantages and hence designer chooses the best depending upon the applications requirement this creates the problem for the applications with time changing requirements. The design presented in this paper provides a solution for such cases by providing simple programmable interface for switching among different techniques with low power and FPGA resource consumption also the proposed design architecture maintains the simplicity without compromising the performance and through simulation we check that with the considerable gain in signal to noise ratio (SNR) and there is minimization of bit e...
This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesse... more This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature.
Transistor density on integrated circuit doubles every two year. For decades, Intel has met this ... more Transistor density on integrated circuit doubles every two year. For decades, Intel has met this challenge and has made Moore's Law a reality. As transistor counts climb so does the ability to increase device complexity and integrate many capabilities onto a chip. With increase in the functional complexity on the chip, accessing of internal sub–circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming difficult, very time consuming and costly process with increasing cost. To reduce the cost of testing of chips by costly Automatic Test Equipment (ATE), Built–In–Self–Test (BIST) technique has emerged as a cheap alternative.
Very large scale integration technology integrates a large system into a single chip. Self checki... more Very large scale integration technology integrates a large system into a single chip. Self checking scheme is becoming an important design technique to full fill the requirements of modern computer systems with full reliability. The paper proposes a analysis of design to implement low cost self testing full adder using duplicated code scheme differential XOR gate for sum and "sharing" transistor technique for carry. The duplicated scheme has the advantage to be totally self-checking for single faults. The designed adder will be self checking for primary inputs and no extra checking circuitry is needed this will reduce the area, hardware and will increase the speed of the adder.
international journal of engineering trends and technology, 2014
In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissi... more In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissipation plays important role in designing of any digital circuit. In earlier many approaches were used to reduce power dissipation. Reversible logic design can also be used for same objective. This approach gaining importance day by day. Arithmetic logic unit is very important part of central processing unit. So it must be fast in term of computations and should dissipate less power. Here a technique is discussed for designing arithmetic and logic unit with the use of reversible gates. Modules are designed using VHDL. Synthesis and simulation is carried out on Xilinx plan ahead 14.4.
Reversible logic is promising as it is able to compute with various applications in very low powe... more Reversible logic is promising as it is able to compute with various applications in very low power like nano- computing for example quantum computing. Reversible circuits are like conventional circuits despite they are build from reversible gates. Reversible circuits, have single, one-to-one mapping between the input and output vectors.Thus all output vectors are permutations of input vectors. A concise review of reversible logic gates basics will be studied. The basic reversible logic gates need to be optimized in reversible logic design and synthesis. Reversible gates need steady inputs for configuration of gate functions and junk outputs that helps in keeping reversibility. Therefore, it is very important to lessen the parameters such as junk bytes, quantum cost and delay in the scheming of reversible circuits. As reversible circuits have tremendous applications in a vairety of emerging technologies such as quantum computing and quantum dot. Consequently this research work would ...
Scaling Associate in Nursingd power reduction trends in future technologies can cause subthreshol... more Scaling Associate in Nursingd power reduction trends in future technologies can cause subthreshold run currents to become an progressively massive part of total power dissipation. the big run power consumption is especially hard in mobile devices, wherever the battery charge capability poses a demanding limitation on the entire energy which will be consumed by a chip. during this technique, sleep transistor square measure placed between the circuits offer and provide rails to show off the run current flow throughout idle time this will be done by victimization one PMOS transistor and one NMOS transistor nonparallel with the transistors of every logic block to make a virtual ground and a virtual power supply. constant estimation victimization town simulation will acquire a comparatively correct estimation of the run distribution; but, this methodology needs an extended simulation time and is therefore computationally expensive. The static and dynamic power of a sleep stack is signifi...
The technological revolution witnessed by the telecommunications industry is leading to the devel... more The technological revolution witnessed by the telecommunications industry is leading to the development of new applications, products and protocols, which in turn solicits widely accessible, highly reliable and high quality networks. To meet the stringent quality and reliability requirements of today's complex communication networks, efficient test methodologies are necessary at all levels. Conventional test methodologies are being constantly challenged by ever-increasing speed and size, which results in high costs associated with test hardware, test generation and test application time. To meet the high quality and reliability requirements for complex communication networks, efficient test methodologies are employed at all levels - system/equipment, board, integrated circuits and so on. Built-in self test (BIST) offers a test methodology where the test functions are embedded into the circuit itself. The advantage of using BIST for complex telecommunication systems are : reduced...
In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The pro... more In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The proposed Multiplier Algorithm takes reduced area than the previous one and the significant delay is also lower than the previous designs. The number of slices in the previous designs is 648 and in our proposed Dadda Multiplier architecture utilizes only 402 slices then area is reduced up to 30%. As shown in the design as well as the simulation results the proposed Multiplier architecture area as well as delay is better.
2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2018
The world peace is disrupting day by day in today’s scenario, increase in terrorism has risen the... more The world peace is disrupting day by day in today’s scenario, increase in terrorism has risen the need of advanced armed technologies in today’s world, there’s no single country in world without dispute, and with disputes comes the riots, uncontrollable mobs, mass fire, bombings etc. This paper is aimed to research into military vehicle, which is capable enough to control a large mob of protesters using microwave beam named as "Heat Ray", which would produce heating sensation on target bodies when incident, and high frequency sound wave named as "Acoustic Gun", which will induce highly vibrating sound beam on the target body, creating a vibrating atmosphere around the target, resulting in nausea and intense headache. The vehicle is also able to diffuse and dispose bomb using a robotic limb with Electromagnetic Pulse (EMP) emitter, which would diffuse the circuit of the live bomb when incidented on it. By converting the constraint conditions of delivery and functions, the model proposed in the paper is not an actual human carrier, but is a manually controlled Unmanned Ground Vehicle (UGV) which is theoretically able to flea the uncontrollable mobs and dispose and diffuse bomb, which is shown in further study.
Abstract— the evolution of compact, light-weight, low-power, and high-quality displays has caus... more Abstract— the evolution of compact, light-weight, low-power, and high-quality displays has caused a large demand for liquid crystal display (LCD) drivers, with features such as low cost, low power dissipation, high speed, and high resolution. we propose a low-Quiescent current Two-Input/Output buffer with class A-B output stage for LCD driver applications. The propose buffer amplifier achieve high speed driving performance, draws a small quiescent current during static operation and offer a rail to rail communication-mode input rang Two-Input/Output buffer with class A-B output stage for LCD driver. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.2 µA static current is consumed in one channel driver. The settling time to settle within 0.15...
The advent of information and communication technologies (ICT), learning has entered into an era ... more The advent of information and communication technologies (ICT), learning has entered into an era of change unparalleled in this generation. The issue is, how theoretical knowledge can apply to real world problem? Academics worldwide have come to the conclusion that traditional learning methods must give way to Digital learning (D-learning). However, in order to change a paradigm, there must be a change in the way that people believe, think and act. A change to Digital learning in engineering education is a paradigm that has its associated challenges. Innovations are required so as to accomplish Digital learning in engineering education. Developing Digital learning tools that will take engineering education beyond traditional capabilities is a part of this challenge. In this paper, I have presented a review on design and development of virtual classroom environment using real-time streaming technology for live and online activity. Student can access the lecture even in presence of mo...
This paper presents design of CMOS voltage reference circuit, by replacing the analog amplifier i... more This paper presents design of CMOS voltage reference circuit, by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit with extended voltage range, and a digital control circuit with minimum supply voltage. The reference voltage circuits are used to adjust the clock frequency to regulate the charge pump to a steady output voltage under a large range of current loads. The parameters such as output resistances and power conversion efficiencies are the performance measures of charge pumps circuits. The propose circuits are design using transmission gate logic. Using transmission gate maximum voltage range is expected and no longer limited by the breakdown voltages of the devices.
Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calc... more Vedic arithmetic is that the traditional system of arithmetic which has a novel technique of calculations supported sixteen Sutras that are discovered by Sri Bharti Krishna Tirthaji. Any processor’s performance depends on 3 vital factors specifically speed, space and power. a higher trade-off between these factors makes the processor, a good one. Multipliers are the usually used architectures within the processor. If the performance of those multipliers is improved then powerful processors is created in future. during this paper, the planned number style supported the sutra‘Urdhva Tiryakbhyam’ of Vedic arithmetic is analyzed and also the performance results of the number are compared with standard multipliers. Extremely economical arithmetic operations are necessary to appreciate the specified performance in several period of time systems and digital image method applications. altogether these applications, one of the necessary arithmetic operations of performed is to multiply and a...
IP Annals of Prosthodontics and Restorative Dentistry, 2020
INTERNATIONAL JOURNAL OF COMMERCE AND BUSINESS MANAGEMENT, 2016
International Journal of Advanced Research in Computer Science and Electronics Engineering, Jan 28, 2013
Image and video compression is one of the major components used in video-telephony, videoconferen... more Image and video compression is one of the major components used in video-telephony, videoconferencing and multimedia-related applications where digital pixel information can comprise considerably large amounts of data. Management of such data can involve significant overhead in computational complexity and data processing. Compression allows efficient utilization of channel bandwidth and storage size. In this paper we describe the design and implementation of a fully pipelined architecture for implementing the JPEG image compression standard. The architecture exploits the principles of pipelining and parallelism in order to obtain high speed and throughput. The design was synthesized using Xilinx9.2i and Spartan 3 FPGAs, and simulation was carried out using ModelSim environment. It has been estimated that the entire architecture can be implemented on a single FPGA to yield a clock rate of about 100 MHz which allow an input rate of 24 bit input RBG.
Computing in Science & Engineering, 2014
These days most microprocessor and microcontroller designs are based on Reduced Instruction Set C... more These days most microprocessor and microcontroller designs are based on Reduced Instruction Set Computer (RISC) core and many operation such as Discrete Cosine transform (DCT) , Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system. This paper represent the design of a Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) system described using VHDL and implement in a Field Programmable Logic Array (FPGA). This RISC is a 20 bit processor.
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE)
The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation ... more The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation of their quantum cost, gate count, garbage outputs and depth of the circuit. The simulation results are obtain edinXilinxISE version 14.1. Reversible logic circuits are designed and implemented using Verilog code. The circuit is beneficial for further designing of reversible digital designs with low power loss. The devices designed through this circuit are expected to have a better performance as compared to the existing circuits.
In this paper, the VHDL design and implementation of BPSK, BASK and BFSK modulator and demodulato... more In this paper, the VHDL design and implementation of BPSK, BASK and BFSK modulator and demodulator with mixed domain performance analysis under different software are presented. The modulators are widely used in communication system either wired or wireless also the applications of these devices are ranging from personal to industrial. Because the every techniques has their own advantages and disadvantages and hence designer chooses the best depending upon the applications requirement this creates the problem for the applications with time changing requirements. The design presented in this paper provides a solution for such cases by providing simple programmable interface for switching among different techniques with low power and FPGA resource consumption also the proposed design architecture maintains the simplicity without compromising the performance and through simulation we check that with the considerable gain in signal to noise ratio (SNR) and there is minimization of bit e...
This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesse... more This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature.
Transistor density on integrated circuit doubles every two year. For decades, Intel has met this ... more Transistor density on integrated circuit doubles every two year. For decades, Intel has met this challenge and has made Moore's Law a reality. As transistor counts climb so does the ability to increase device complexity and integrate many capabilities onto a chip. With increase in the functional complexity on the chip, accessing of internal sub–circuits of chip for testing purposes is becoming very difficult, as they are not directly accessible through primary inputs. So, the testing of chip is also becoming difficult, very time consuming and costly process with increasing cost. To reduce the cost of testing of chips by costly Automatic Test Equipment (ATE), Built–In–Self–Test (BIST) technique has emerged as a cheap alternative.
Very large scale integration technology integrates a large system into a single chip. Self checki... more Very large scale integration technology integrates a large system into a single chip. Self checking scheme is becoming an important design technique to full fill the requirements of modern computer systems with full reliability. The paper proposes a analysis of design to implement low cost self testing full adder using duplicated code scheme differential XOR gate for sum and "sharing" transistor technique for carry. The duplicated scheme has the advantage to be totally self-checking for single faults. The designed adder will be self checking for primary inputs and no extra checking circuitry is needed this will reduce the area, hardware and will increase the speed of the adder.
international journal of engineering trends and technology, 2014
In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissi... more In modern Era of circuit designing, complexity of circuit increases day by day. Hence power dissipation plays important role in designing of any digital circuit. In earlier many approaches were used to reduce power dissipation. Reversible logic design can also be used for same objective. This approach gaining importance day by day. Arithmetic logic unit is very important part of central processing unit. So it must be fast in term of computations and should dissipate less power. Here a technique is discussed for designing arithmetic and logic unit with the use of reversible gates. Modules are designed using VHDL. Synthesis and simulation is carried out on Xilinx plan ahead 14.4.
Reversible logic is promising as it is able to compute with various applications in very low powe... more Reversible logic is promising as it is able to compute with various applications in very low power like nano- computing for example quantum computing. Reversible circuits are like conventional circuits despite they are build from reversible gates. Reversible circuits, have single, one-to-one mapping between the input and output vectors.Thus all output vectors are permutations of input vectors. A concise review of reversible logic gates basics will be studied. The basic reversible logic gates need to be optimized in reversible logic design and synthesis. Reversible gates need steady inputs for configuration of gate functions and junk outputs that helps in keeping reversibility. Therefore, it is very important to lessen the parameters such as junk bytes, quantum cost and delay in the scheming of reversible circuits. As reversible circuits have tremendous applications in a vairety of emerging technologies such as quantum computing and quantum dot. Consequently this research work would ...
Scaling Associate in Nursingd power reduction trends in future technologies can cause subthreshol... more Scaling Associate in Nursingd power reduction trends in future technologies can cause subthreshold run currents to become an progressively massive part of total power dissipation. the big run power consumption is especially hard in mobile devices, wherever the battery charge capability poses a demanding limitation on the entire energy which will be consumed by a chip. during this technique, sleep transistor square measure placed between the circuits offer and provide rails to show off the run current flow throughout idle time this will be done by victimization one PMOS transistor and one NMOS transistor nonparallel with the transistors of every logic block to make a virtual ground and a virtual power supply. constant estimation victimization town simulation will acquire a comparatively correct estimation of the run distribution; but, this methodology needs an extended simulation time and is therefore computationally expensive. The static and dynamic power of a sleep stack is signifi...
The technological revolution witnessed by the telecommunications industry is leading to the devel... more The technological revolution witnessed by the telecommunications industry is leading to the development of new applications, products and protocols, which in turn solicits widely accessible, highly reliable and high quality networks. To meet the stringent quality and reliability requirements of today's complex communication networks, efficient test methodologies are necessary at all levels. Conventional test methodologies are being constantly challenged by ever-increasing speed and size, which results in high costs associated with test hardware, test generation and test application time. To meet the high quality and reliability requirements for complex communication networks, efficient test methodologies are employed at all levels - system/equipment, board, integrated circuits and so on. Built-in self test (BIST) offers a test methodology where the test functions are embedded into the circuit itself. The advantage of using BIST for complex telecommunication systems are : reduced...
In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The pro... more In this paper area efficient Multiplier architecture is developed using Dadda Multiplier. The proposed Multiplier Algorithm takes reduced area than the previous one and the significant delay is also lower than the previous designs. The number of slices in the previous designs is 648 and in our proposed Dadda Multiplier architecture utilizes only 402 slices then area is reduced up to 30%. As shown in the design as well as the simulation results the proposed Multiplier architecture area as well as delay is better.