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Papers by victor zyuban

Research paper thumbnail of Session details: Energy efficient architectural techniques

Research paper thumbnail of Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques

Research paper thumbnail of Reduced Leakage Banked Wordline Header

Research paper thumbnail of Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms

Research paper thumbnail of The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

Research paper thumbnail of Clocking strategies and scannable latches for low power appliacations

Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01, 2001

This paper covers a range of issues in the design of clocking schemes for low-power applications.... more This paper covers a range of issues in the design of clocking schemes for low-power applications. First we revisit, extend and improve the power-performance optimization methodology for latches, attempting to make it more formal and comprehensive. Data switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of energy-efficient family of configurations is introduced to make the comparison of different latch styles in the power-performance space more fair, also the power of the clock distribution is taken into account. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power LSSD extension to single-phase latches is proposed, and results of a comparative study of LSSDscannable latches are shown, supported by experimental data measured on a 0:18 test chip.

Research paper thumbnail of Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels

Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02, 2002

Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which ... more Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity (η), which is useful for evaluating issues that affect both circuits and architecture. Analyzing data for actual designs we show how to measure the introduced parameters and discuss variations between observed results and common theoretical assumptions. For a power-efficient design we derive relations for η and supply voltage V under progressively more general situations, and incorporate η into a prior art architectural energy-efficiency criterion. Then, a more general relation is derived for the optimal balance between the architectural complexity, hardware intensity and power supply. Modified forms for these relations are obtained in special cases where the supply voltage is constrained or when clock gating is disallowed.

Research paper thumbnail of Unified architecture level energy-efficiency metric

Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02, 2002

The development of power-efficient microprocessors presents the need to consider power consumptio... more The development of power-efficient microprocessors presents the need to consider power consumption at early stages of design, particularly at the ISA and microarchitecture definition stages, where the potential for power savings is more significant than at lowerlevel stages, and the opportunity for making power-performance tradeoffs is the largest. Design modifications to the ISA and microarchitecture, however, affect most (if not all) parameters of the design, including architectural speed, code density, clocking rate and power. A reliable metric is required to make knowledgeable power-performance tradeoffs in this multi-dimensional space. This paper derives a unified energy-efficiency metric for evaluating ISA and microarchitecture features, which subsumes other commonly used power-performance metrics as special cases of a more general equation. This new metric is derived based on an analysis of a multi-dimensional power optimization problem, and the resulting formula involves only relative changes in the characteristics of a processor, enabling its application at the early stages of the design.

Research paper thumbnail of Predicting microprocessor lifetime reliability using architecture-level structure-aware techniques

Research paper thumbnail of Apparatus for multiplication of data in two's complement and unsigned magnitude formats

Research paper thumbnail of Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip

Research paper thumbnail of Transition Graph Methodology for Estimating Power Dissipation and its Application to Latch Design

Research paper thumbnail of A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)

Lecture Notes in Computer Science, 2010

In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for... more In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process using state-of-the-art non-linear optimization solvers and fast circuit simulators. Node switching activities and LDC are integrated into the EinsTuner framework as parameter inputs to the FPR tuning mode. In FPR mode, the power is minimized using gate width reduction with respect to power properties of the node. The FPR methodology is evaluated on next generation microprocessor circuit designs. Power reduction results are compared with the results from the existing EinsTuner tuning methodology. The results show improvement in power reduction with the FPR optimization mode.

Research paper thumbnail of Session 8 overview: Low-power digital techniques: Energy-efficient digital

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015

Energy efficiency is becoming the main design driver for both small embedded microcontrollers, as... more Energy efficiency is becoming the main design driver for both small embedded microcontrollers, as well as multicore platforms. This session presents a wide range of low-power digital-design techniques implemented in complete ultra-low-power microcontrollers for the Internet-of-Things (IoT), as well as in SoC building blocks exploiting fine-grain DVFS. The record-low power operation of the presented ARM and TI cores will prolong battery life in many IoT applications and enable energy-harvesting operations. These papers achieve both low-active power consumption, as well as incorporating techniques for efficient full-state retention. On the SoC side, innovative on-chip voltage and frequency regulation techniques enable operation across a wide range of supply voltages and PVT variations. This enables operation at reduced voltages and lower power. Novel voltage regulators increase energy efficiency and reduce voltage droops on the power rails caused by variations in the current consumptions of the cores.

Research paper thumbnail of Low power integrated scan-retention mechanism

Proceedings of the International Symposium on Low Power Electronics and Design, 2002

This paper presents a methodology for unifying the scan mechanism and data retention in latches w... more This paper presents a methodology for unifying the scan mechanism and data retention in latches which leads to scannable latches with the data retention capability achieved at a very low power overhead during the active mode. A detailed analysis of power and area overhead is presented, with layout examples for various common latch styles. Implications of using different power gating techniques for reducing leakage during sleep mode on the design of retention latches are considered, including well biasing for leakage control and sharing wells between gated logic and retention latch devices.

Research paper thumbnail of Power–Performance Trade-Offs in Design of SoCs

Low-Power Processors and Systems on Chips, 2005

Research paper thumbnail of Optimizing pipelines for power and performance

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.

During the concept phase and definition of next generation high-end processors, power and perform... more During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical power-performance model to derive optimal pipeline depth for a superscalar processor. The results are validated and further refined using detailed simulation based analysis. As part of the power-modeling methodology, we have developed equations that model the variation of energy as a function of pipeline depth. Our results using a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models.

Research paper thumbnail of A Framework for Architecture-Level Lifetime Reliability Modeling

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007

Page 1. A Framework for Architecture-level Lifetime Reliability Modeling Jeonghee Shin†, Victor Z... more Page 1. A Framework for Architecture-level Lifetime Reliability Modeling Jeonghee Shin†, Victor Zyuban, Zhigang Hu, Jude A. Rivers and Pradip Bose IBM TJ Watson Research Center Yorktown Heights, NY 10598 {zyuban, zhigangh, jarivers and pbose}@us.ibm.com Abstract ...

Research paper thumbnail of Processor with demand-driven clock throttling power reduction

Research paper thumbnail of Method and system of peak power enforcement via autonomous token-based control and management

Research paper thumbnail of Session details: Energy efficient architectural techniques

Research paper thumbnail of Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques

Research paper thumbnail of Reduced Leakage Banked Wordline Header

Research paper thumbnail of Method and apparatus for extending lifetime reliability of digital logic devices through reversal of aging mechanisms

Research paper thumbnail of The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

Research paper thumbnail of Clocking strategies and scannable latches for low power appliacations

Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01, 2001

This paper covers a range of issues in the design of clocking schemes for low-power applications.... more This paper covers a range of issues in the design of clocking schemes for low-power applications. First we revisit, extend and improve the power-performance optimization methodology for latches, attempting to make it more formal and comprehensive. Data switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of energy-efficient family of configurations is introduced to make the comparison of different latch styles in the power-performance space more fair, also the power of the clock distribution is taken into account. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power LSSD extension to single-phase latches is proposed, and results of a comparative study of LSSDscannable latches are shown, supported by experimental data measured on a 0:18 test chip.

Research paper thumbnail of Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels

Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02, 2002

Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which ... more Evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity (η), which is useful for evaluating issues that affect both circuits and architecture. Analyzing data for actual designs we show how to measure the introduced parameters and discuss variations between observed results and common theoretical assumptions. For a power-efficient design we derive relations for η and supply voltage V under progressively more general situations, and incorporate η into a prior art architectural energy-efficiency criterion. Then, a more general relation is derived for the optimal balance between the architectural complexity, hardware intensity and power supply. Modified forms for these relations are obtained in special cases where the supply voltage is constrained or when clock gating is disallowed.

Research paper thumbnail of Unified architecture level energy-efficiency metric

Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02, 2002

The development of power-efficient microprocessors presents the need to consider power consumptio... more The development of power-efficient microprocessors presents the need to consider power consumption at early stages of design, particularly at the ISA and microarchitecture definition stages, where the potential for power savings is more significant than at lowerlevel stages, and the opportunity for making power-performance tradeoffs is the largest. Design modifications to the ISA and microarchitecture, however, affect most (if not all) parameters of the design, including architectural speed, code density, clocking rate and power. A reliable metric is required to make knowledgeable power-performance tradeoffs in this multi-dimensional space. This paper derives a unified energy-efficiency metric for evaluating ISA and microarchitecture features, which subsumes other commonly used power-performance metrics as special cases of a more general equation. This new metric is derived based on an analysis of a multi-dimensional power optimization problem, and the resulting formula involves only relative changes in the characteristics of a processor, enabling its application at the early stages of the design.

Research paper thumbnail of Predicting microprocessor lifetime reliability using architecture-level structure-aware techniques

Research paper thumbnail of Apparatus for multiplication of data in two's complement and unsigned magnitude formats

Research paper thumbnail of Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip

Research paper thumbnail of Transition Graph Methodology for Estimating Power Dissipation and its Application to Latch Design

Research paper thumbnail of A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)

Lecture Notes in Computer Science, 2010

In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for... more In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process using state-of-the-art non-linear optimization solvers and fast circuit simulators. Node switching activities and LDC are integrated into the EinsTuner framework as parameter inputs to the FPR tuning mode. In FPR mode, the power is minimized using gate width reduction with respect to power properties of the node. The FPR methodology is evaluated on next generation microprocessor circuit designs. Power reduction results are compared with the results from the existing EinsTuner tuning methodology. The results show improvement in power reduction with the FPR optimization mode.

Research paper thumbnail of Session 8 overview: Low-power digital techniques: Energy-efficient digital

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015

Energy efficiency is becoming the main design driver for both small embedded microcontrollers, as... more Energy efficiency is becoming the main design driver for both small embedded microcontrollers, as well as multicore platforms. This session presents a wide range of low-power digital-design techniques implemented in complete ultra-low-power microcontrollers for the Internet-of-Things (IoT), as well as in SoC building blocks exploiting fine-grain DVFS. The record-low power operation of the presented ARM and TI cores will prolong battery life in many IoT applications and enable energy-harvesting operations. These papers achieve both low-active power consumption, as well as incorporating techniques for efficient full-state retention. On the SoC side, innovative on-chip voltage and frequency regulation techniques enable operation across a wide range of supply voltages and PVT variations. This enables operation at reduced voltages and lower power. Novel voltage regulators increase energy efficiency and reduce voltage droops on the power rails caused by variations in the current consumptions of the cores.

Research paper thumbnail of Low power integrated scan-retention mechanism

Proceedings of the International Symposium on Low Power Electronics and Design, 2002

This paper presents a methodology for unifying the scan mechanism and data retention in latches w... more This paper presents a methodology for unifying the scan mechanism and data retention in latches which leads to scannable latches with the data retention capability achieved at a very low power overhead during the active mode. A detailed analysis of power and area overhead is presented, with layout examples for various common latch styles. Implications of using different power gating techniques for reducing leakage during sleep mode on the design of retention latches are considered, including well biasing for leakage control and sharing wells between gated logic and retention latch devices.

Research paper thumbnail of Power–Performance Trade-Offs in Design of SoCs

Low-Power Processors and Systems on Chips, 2005

Research paper thumbnail of Optimizing pipelines for power and performance

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.

During the concept phase and definition of next generation high-end processors, power and perform... more During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPI-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical power-performance model to derive optimal pipeline depth for a superscalar processor. The results are validated and further refined using detailed simulation based analysis. As part of the power-modeling methodology, we have developed equations that model the variation of energy as a function of pipeline depth. Our results using a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 FO4. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models.

Research paper thumbnail of A Framework for Architecture-Level Lifetime Reliability Modeling

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007

Page 1. A Framework for Architecture-level Lifetime Reliability Modeling Jeonghee Shin†, Victor Z... more Page 1. A Framework for Architecture-level Lifetime Reliability Modeling Jeonghee Shin†, Victor Zyuban, Zhigang Hu, Jude A. Rivers and Pradip Bose IBM TJ Watson Research Center Yorktown Heights, NY 10598 {zyuban, zhigangh, jarivers and pbose}@us.ibm.com Abstract ...

Research paper thumbnail of Processor with demand-driven clock throttling power reduction

Research paper thumbnail of Method and system of peak power enforcement via autonomous token-based control and management