Berna Ors Yalcin | Istanbul Technical University (original) (raw)

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Papers by Berna Ors Yalcin

Research paper thumbnail of Design of core blocks and implementation on a programmable logic controller for a train signalization system

2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

Research paper thumbnail of FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m)

2008 International Conference on Reconfigurable Computing and FPGAs, 2008

This paper describes a FPGA implementation of The EC can take many forms. In the context of this ... more This paper describes a FPGA implementation of The EC can take many forms. In the context of this paper, an elliptic curve cryptosystem. Such systems are becoming the EC will be constrained to the form given by (1) as provided increasingly popular as they provide the highest strength per by the NIST' [4]. bit of any cryptosystem commonly used today. The cryptosystem was built exploiting the wNAF representation of the private key

Research paper thumbnail of Radio Frequency Identification: Security and Privacy Issues

Lecture Notes in Computer Science, 2014

... Dominikus Ozgur Ergul Albert Fernndez-Mir Flavio Garcia Yoshikazu Hanatani Michael Hutter Orh... more ... Dominikus Ozgur Ergul Albert Fernndez-Mir Flavio Garcia Yoshikazu Hanatani Michael Hutter Orhun Kara Suleyman Kardas Timo Kasper Selcuk Kavut Yutaka Kawai Chong-Hee Kim Mehmet Sabır Kiraz Miroslav Knezevic ... 258 Elif Bilge Kavun and Tolga Yalcin Author Index ...

Research paper thumbnail of Final report of European project number IST-1999-12324, named New European Schemes for Signatures, Integrity, and Encryption

Research paper thumbnail of Secure voice communication via GSM network

ABSTRACT In this study, a system is developed which communicates through GSM mobile phones and pr... more ABSTRACT In this study, a system is developed which communicates through GSM mobile phones and provides protection for interviews against third parties including with service providers developed. GSM line is sensitive to human speech to be more efficient and provide more quality for transmission. In addition, a tool should be used to compress speech to transmit speech over GSM. For these reasons, speech cannot be transmitted to the GSM line directly after encrypted. In this study, the encrypted speech which is a digital data stream, formed speech like waveform by the designed coder to transmit through the GSM line. FPGA implementation of AES is used for encryption of digital data stream. Desired speech characteristics are obtained by scanning the database of NTIMIT, and then LBG algorithm is used to design codebooks which include speech parameters. A coder is designed to synthesize speech like waveforms from the encrypted digital data stream.

Research paper thumbnail of Final report of NESSIE, New European Schemes for Signatures, Integrity, and Encryption

Research paper thumbnail of Final report of European project IST-1999-12324: New European schemes for signatures, integrity, and encryption

Research paper thumbnail of Performance of optimized implementations of the NESSIE primitives

Research paper thumbnail of Power Analysis of an FPGA (Implementation of Rijndael: Is Pipelining a DPA Countermeasure?)

Lecture notes in computer …, 2004

Abstract. Since their publication in 1998, power analysis attacks have attracted significant atte... more Abstract. Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to different kinds of (unpro-tected) implementations of symmetric and public-key encryption schemes. ...

Research paper thumbnail of New European Schemes for Signatures, Integrity, and Encryption

Research paper thumbnail of Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques

2016 24th Signal Processing and Communication Application Conference (SIU), 2016

Research paper thumbnail of RPL version number attacks: In-depth study

NOMS 2016 - 2016 IEEE/IFIP Network Operations and Management Symposium, 2016

Research paper thumbnail of Fault tolerant register file design for MIPS AES-crypto microprocessor

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2015

Research paper thumbnail of Internet-of-Things security: Denial of service attacks

2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

Research paper thumbnail of Low-cost implementations of NTRU for pervasive security

2008 International Conference on Application-Specific Systems, Architectures and Processors, 2008

NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an a... more NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design that is suitable for pervasive security applications such as RFIDs and sensor nodes. We have designed two architectures, one is only capable of encryption and the other one performs both encryption and decryption. The strategy for the designs includes clock gating of registers, operand isolation and precomputation. This work is also the first one to present a complete NTRU design with encryption/decryption circuitry. Our encryption-only NTRU design has a gate-count of 2.8 kgates and dynamic power consumption of 1.72 µW . Moreover, encryption-decryption NTRU design consumes about 6 µW dynamic power and consists of 10.5 kgates.

Research paper thumbnail of Privacy-Friendly Authentication in RFID Systems: On Sublinear Protocols Based on Symmetric-Key Cryptography

IEEE Transactions on Mobile Computing, 2000

Abstract In this paper, we provide a comprehensive analysis of privacy-friendly authentication pr... more Abstract In this paper, we provide a comprehensive analysis of privacy-friendly authentication protocols devoted to RFID that:(1) are based on well-established symmetric-key cryptographic building blocks;(2) require a reader complexity lower than O (N) where N is the number of provers in the system. These two properties are sine qua non conditions for deploying privacy-friendly authentication protocols in large-scale applications, eg, access control in mass transportation. We describe existing protocols fulfilling these requirements ...

Research paper thumbnail of Security and performance analysis of ARIA

Final report, KU …, Jan 1, 2004

Research paper thumbnail of Flexible hardware design for RSA and elliptic curve cryptosystems

Topics in Cryptology–CT-RSA 2004, Jan 1, 2004

This paper presents a scalable hardware implementation of both commonly used public key cryptosys... more This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless applications, up to a very big design (more than 100 Kgates) used for network security. In latter option it can include a few dedicated large number arithmetic units each of which is a systolic array performing the Montgomery Modular Multiplication (MMM). The bound on the Montgomery parameter has been optimized to facilitate more secure ECC point operations. Furthermore, we present a new possibility for CRT scheme which is less vulnerable to side-channel attacks.

Research paper thumbnail of An FPGA implementation of an elliptic curve processor GF (2 m)

Proceedings of the 14th ACM Great …, Jan 1, 2004

This paper describes a hardware implementation of an arithmetic processor which is efficient for ... more This paper describes a hardware implementation of an arithmetic processor which is efficient for elliptic curve (EC) cryptosystems, which are becoming increasingly popular as an alternative for public key cryptosystems based on factoring. The modular multiplication is implemented using a Montgomery modular multiplication in a systolic array architecture, which has the advantage that the clock frequency becomes independent of the bit length m.

Research paper thumbnail of Power analysis attacks against FPGA implementations of the DES

Field Programmable Logic …, Jan 1, 2004

Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper res... more Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper resistant environments. However, physical implementations can be extremely difficult to control and may result in the unintended leakage of side-channel information. In power analysis attacks, it is assumed that the power consumption is correlated to the data that is being processed. An attacker may therefore recover secret information by simply monitoring the power consumption of a device. Several articles have investigated power attacks in the context of smart card implementations. While FPGAs are becoming increasingly popular for cryptographic applications, there are only a few articles that assess their vulnerability to physical attacks. In this article, we demonstrate the specific properties of FPGAs w.r.t. Differential Power Analysis (DPA). First we emphasize that the original attack by Kocher et al. and the improvements by Brier et al. do not apply directly to FPGAs because their physical behavior differs substantially from that of smart cards. Then we generalize the DPA attack to FPGAs and provide strong evidence that FPGA implementations of the Data Encryption Standard (DES) are vulnerable to such attacks.

Research paper thumbnail of Design of core blocks and implementation on a programmable logic controller for a train signalization system

2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

Research paper thumbnail of FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m)

2008 International Conference on Reconfigurable Computing and FPGAs, 2008

This paper describes a FPGA implementation of The EC can take many forms. In the context of this ... more This paper describes a FPGA implementation of The EC can take many forms. In the context of this paper, an elliptic curve cryptosystem. Such systems are becoming the EC will be constrained to the form given by (1) as provided increasingly popular as they provide the highest strength per by the NIST' [4]. bit of any cryptosystem commonly used today. The cryptosystem was built exploiting the wNAF representation of the private key

Research paper thumbnail of Radio Frequency Identification: Security and Privacy Issues

Lecture Notes in Computer Science, 2014

... Dominikus Ozgur Ergul Albert Fernndez-Mir Flavio Garcia Yoshikazu Hanatani Michael Hutter Orh... more ... Dominikus Ozgur Ergul Albert Fernndez-Mir Flavio Garcia Yoshikazu Hanatani Michael Hutter Orhun Kara Suleyman Kardas Timo Kasper Selcuk Kavut Yutaka Kawai Chong-Hee Kim Mehmet Sabır Kiraz Miroslav Knezevic ... 258 Elif Bilge Kavun and Tolga Yalcin Author Index ...

Research paper thumbnail of Final report of European project number IST-1999-12324, named New European Schemes for Signatures, Integrity, and Encryption

Research paper thumbnail of Secure voice communication via GSM network

ABSTRACT In this study, a system is developed which communicates through GSM mobile phones and pr... more ABSTRACT In this study, a system is developed which communicates through GSM mobile phones and provides protection for interviews against third parties including with service providers developed. GSM line is sensitive to human speech to be more efficient and provide more quality for transmission. In addition, a tool should be used to compress speech to transmit speech over GSM. For these reasons, speech cannot be transmitted to the GSM line directly after encrypted. In this study, the encrypted speech which is a digital data stream, formed speech like waveform by the designed coder to transmit through the GSM line. FPGA implementation of AES is used for encryption of digital data stream. Desired speech characteristics are obtained by scanning the database of NTIMIT, and then LBG algorithm is used to design codebooks which include speech parameters. A coder is designed to synthesize speech like waveforms from the encrypted digital data stream.

Research paper thumbnail of Final report of NESSIE, New European Schemes for Signatures, Integrity, and Encryption

Research paper thumbnail of Final report of European project IST-1999-12324: New European schemes for signatures, integrity, and encryption

Research paper thumbnail of Performance of optimized implementations of the NESSIE primitives

Research paper thumbnail of Power Analysis of an FPGA (Implementation of Rijndael: Is Pipelining a DPA Countermeasure?)

Lecture notes in computer …, 2004

Abstract. Since their publication in 1998, power analysis attacks have attracted significant atte... more Abstract. Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to different kinds of (unpro-tected) implementations of symmetric and public-key encryption schemes. ...

Research paper thumbnail of New European Schemes for Signatures, Integrity, and Encryption

Research paper thumbnail of Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques

2016 24th Signal Processing and Communication Application Conference (SIU), 2016

Research paper thumbnail of RPL version number attacks: In-depth study

NOMS 2016 - 2016 IEEE/IFIP Network Operations and Management Symposium, 2016

Research paper thumbnail of Fault tolerant register file design for MIPS AES-crypto microprocessor

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2015

Research paper thumbnail of Internet-of-Things security: Denial of service attacks

2015 23nd Signal Processing and Communications Applications Conference (SIU), 2015

Research paper thumbnail of Low-cost implementations of NTRU for pervasive security

2008 International Conference on Application-Specific Systems, Architectures and Processors, 2008

NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an a... more NTRU is a public-key cryptosystem based on the shortest vector problem in a lattice which is an alternative to RSA and ECC. This work presents a compact and low power NTRU design that is suitable for pervasive security applications such as RFIDs and sensor nodes. We have designed two architectures, one is only capable of encryption and the other one performs both encryption and decryption. The strategy for the designs includes clock gating of registers, operand isolation and precomputation. This work is also the first one to present a complete NTRU design with encryption/decryption circuitry. Our encryption-only NTRU design has a gate-count of 2.8 kgates and dynamic power consumption of 1.72 µW . Moreover, encryption-decryption NTRU design consumes about 6 µW dynamic power and consists of 10.5 kgates.

Research paper thumbnail of Privacy-Friendly Authentication in RFID Systems: On Sublinear Protocols Based on Symmetric-Key Cryptography

IEEE Transactions on Mobile Computing, 2000

Abstract In this paper, we provide a comprehensive analysis of privacy-friendly authentication pr... more Abstract In this paper, we provide a comprehensive analysis of privacy-friendly authentication protocols devoted to RFID that:(1) are based on well-established symmetric-key cryptographic building blocks;(2) require a reader complexity lower than O (N) where N is the number of provers in the system. These two properties are sine qua non conditions for deploying privacy-friendly authentication protocols in large-scale applications, eg, access control in mass transportation. We describe existing protocols fulfilling these requirements ...

Research paper thumbnail of Security and performance analysis of ARIA

Final report, KU …, Jan 1, 2004

Research paper thumbnail of Flexible hardware design for RSA and elliptic curve cryptosystems

Topics in Cryptology–CT-RSA 2004, Jan 1, 2004

This paper presents a scalable hardware implementation of both commonly used public key cryptosys... more This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless applications, up to a very big design (more than 100 Kgates) used for network security. In latter option it can include a few dedicated large number arithmetic units each of which is a systolic array performing the Montgomery Modular Multiplication (MMM). The bound on the Montgomery parameter has been optimized to facilitate more secure ECC point operations. Furthermore, we present a new possibility for CRT scheme which is less vulnerable to side-channel attacks.

Research paper thumbnail of An FPGA implementation of an elliptic curve processor GF (2 m)

Proceedings of the 14th ACM Great …, Jan 1, 2004

This paper describes a hardware implementation of an arithmetic processor which is efficient for ... more This paper describes a hardware implementation of an arithmetic processor which is efficient for elliptic curve (EC) cryptosystems, which are becoming increasingly popular as an alternative for public key cryptosystems based on factoring. The modular multiplication is implemented using a Montgomery modular multiplication in a systolic array architecture, which has the advantage that the clock frequency becomes independent of the bit length m.

Research paper thumbnail of Power analysis attacks against FPGA implementations of the DES

Field Programmable Logic …, Jan 1, 2004

Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper res... more Cryptosystem designers frequently assume that secret parameters will be manipulated in tamper resistant environments. However, physical implementations can be extremely difficult to control and may result in the unintended leakage of side-channel information. In power analysis attacks, it is assumed that the power consumption is correlated to the data that is being processed. An attacker may therefore recover secret information by simply monitoring the power consumption of a device. Several articles have investigated power attacks in the context of smart card implementations. While FPGAs are becoming increasingly popular for cryptographic applications, there are only a few articles that assess their vulnerability to physical attacks. In this article, we demonstrate the specific properties of FPGAs w.r.t. Differential Power Analysis (DPA). First we emphasize that the original attack by Kocher et al. and the improvements by Brier et al. do not apply directly to FPGAs because their physical behavior differs substantially from that of smart cards. Then we generalize the DPA attack to FPGAs and provide strong evidence that FPGA implementations of the Data Encryption Standard (DES) are vulnerable to such attacks.