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Papers by sathish anchula

To increase the performance and reliability of highly integrated circuits like DSP processors, Mi... more To increase the performance and reliability of highly integrated circuits like DSP processors, Microprocessors and SoCs, transistors sizes are continues to scale towards Deep Submicron and Very Deep Submicron dimensions . As more and more transistors are packed on the chip to increase the functionality more metal layers are being added to the integrated chips. Hence the performance of the chips depends more on the performance of global interconnect and on-chip busses than gate performance. The performance of the global interconnects and on-chip data busses is limited by switching activity, energy dissipation and noise such as crosstalk, leakage, supply noise and process variations etc. which are the side effects of the technology scaling. To increase the performance of overall system it is necessary to control and reduce these technology scaling effects on on-chip data buses. One of the favorable techniques to increase the efficiency of the data buses is to encode the data on the onchip bus. Data encoding technique is the promising method to increase the performance of the data bus and hence overall system performance. Hence high performance data bus encoding technique is propose which reduces switching activity, transition energy dissipation, crosstalk and crosstalk delay. The proposed method reduces the switching activity by around 23%, energy dissipation by 46%, 6C, 5C and 4C type crosstalk by around 89%, 73% and 31% respectively and crosstalk delay by around 44% to 50% compare to unencoded data.

In many digital processors, the power dissipation in apart . In this method, the total number of ... more In many digital processors, the power dissipation in apart . In this method, the total number of transitions the bus is a major part of the total chip power dissipation. For occurring between the newly arrived data and the present CMOS circuits most power is dissipated as a dynamic power data on the bus is first calculated. If this number is more for charging and discharging node capacitances. In non deep than half the number of sub-micron technology, these capacitances are mainly the substrate capacitances of the bus wires where as in deep submicron technology inter wire capacitance also contribute to total capacitance. The main objective of this paper is to explain a new algorithm called Bus Regrouping Method to reduce coupling transitions. As a consequence the power dissipation due to the coupling capacitance or inter wire capacitance in deep sub-micron technology is optimized.

A.P. PG Student RGMCET, Nandyal, A.P.

A.P PG student RGMCET, Nandyal, A.P.

In Very Deep-submicron (VDSM) systems, the scaling of ULSI ICs has increased the sensitivity of C... more In Very Deep-submicron (VDSM) systems, the scaling of ULSI ICs has increased the sensitivity of CMOS technology to cause various noise mechanismssuch as power supply noise, crosstalk noise, leakage noise, etc. In VDSM technology distance between the data bus lines is reduced, so coupling capacitance is dominating factor. Unfortunately, in VDSM systems, the coupling capacitance is of magnitude several times larger than the loading capacitance. The coupling capacitance causes logical malfunction, delay faults, and power consumption on long onchip data buses .An important effect of the coupling capacitance is Cross talk. Crosstalk is mainly dependent on several factors: drive strength, wire length/spacing, edge rate and propagation duration. The crosstalk noise produces from the coupling capacitance. Such faults may affect data on data bus. To avoid this condition and to guarantee signal integrity on the on-chip communication, a fault tolerant bus can be adopted. This could be achieved by implementing error-correcting codes (ECCs), providing on-line correction and do not require data retransmission. The 4,8,16,and 32-bit data bus is implemented in 180nm, 120nm,and 65nm technologies using Bsim4 model. For reliable transmission of the data ECC techniques is placed on the data bus. We employed a Hamming code and Dual rail as ECC for 4,8,16 and 32-bit fault tolerant data bus. This is implemented in 180nm, 120nm and 65nm technology. The simulation results show that Average power varies from0.737mw to 0.176mw, and Maximum delay varies from 0.143nsec to 0.077nsec,for hamming 4 bit ECC, Average power varies from 2.135mw to 0.365mw and Maximum delay varies from 0.385nsec to 0.192nsec for hamming 8 bit ECC, Average power varies from 2.288mw to 0.377mw and Maximum delay varies from 0.721nsec to 0.353nsec for hamming 16 bit ECC, Average power varies from 3.064mw to 0.437mw and Maximum delay varies from 1.562nsec to 0.796nsec for hamming 32 bit ECC. The simulation results show that Average power varies from0.206mw to 0.0459mw, and Maximum delay varies from 0.241nsec to 0.133nsec,for dual rail 4 bit ECC, Average power varies from 0.417mw to 0.0768mw and Maximum delay varies from 0.479nsec to 0.262nsec for dual rail 8 bit ECC, Average power varies from 0.726mw to 0.156mw and Maximum delay varies from 1.026nsec to 0.554nsec for dual rail 16 bit ECC, Average power varies from 0.926mw to 0.108mw and Maximum delay varies from 2.129nsec to 1.145nsec for dual rail 32 bit ECC respectively.

Crosstalk has become the great challenge to the design community in Deep-submicron (DSM) and Very... more Crosstalk has become the great challenge to the design community in Deep-submicron (DSM) and Very Deepsubmicron (VDSM) technologies. As the portion of silicon area for interconnects and buses is dominating, crosstalk effect also dominates in deciding the reliability and performance of the SoCs and many types of processors. These interconnect and buses are prone to errors due to crosstalk. The major part of the crosstalk is due to coupling transitions occurring on the data bus and interconnects when signals are transmitted. One of the favorable techniques to reduce the crosstalk is to reduce the coupling transitions. Bus encoding technique is the promising method to reduce the crosstalk. Hence an efficient Crosstalk reduction data bus encoding scheme is proposed which can reduce the 6C, 5C and 4C crosstalk for 64-bit data bus around 88%, 68% and 24% respectively, for 32-bit data bus around 89%, 74% and 32% respectively and 16-bit data bus by 93%, 71% and 19% respectively.

In Deep-submicron (DSM) systems, the crosstalk effect on onchip data buses and interconnects dict... more In Deep-submicron (DSM) systems, the crosstalk effect on onchip data buses and interconnects dictates the overall performance and reliability of the highly integrated systems. In many digital processors and SoC the reliable transfer of the information over the data bus is crucial for the proper operation of a particular system. Hence ECC techniques are used on data buses for reliable transfer of the information. Employing the ECC on data buses eventually increases the switching activity that affects the power consumption and delay of the system. Reducing the power dissipation of the VLSI chip is one of the major challenges in the DSM technology. One of the best techniques to reduce the transitions is to use encode and decoder along with the ECC on the data bus. Hence an efficient switching activity reduction technique is proposed for fault tolerant data bus which can reduce the overall transitions. The proposed encoding technique reduces the switching activity by 18% to 22.5%. Its efficiency is 8% to 15% more compare to others encoding techniques.

In Deep-submicron (DSM) systems, the coupling effect on onchip data buses and interconnects plays... more In Deep-submicron (DSM) systems, the coupling effect on onchip data buses and interconnects plays an important role in overall performance and reliability of the VLSI systems. In many digital processors and SoC the switching activity results into dynamic power dissipation on t he data buses and interconnects which is a major part of the total chip power dissipation. Switching activity is due to self transitions and coupling transitions. Reducing the power dissipation of the VLSI chip is one of the major challenges in the DSM technology. One of the best techniques to reduce the transitions is to encode the data on the data bus. Hence an efficient switching activity reduction technique is proposed which can reduce the overall transitions. The proposed encoding technique reduces the coupling transition by 29% to 33%, self transitions by 4% to 19% and overall transitions by 22% to 27%. Its efficiency is 10% to 17% more compare to others encoding techniques.

As CMOS VLSI integration continues with shrinking feature size, the energy dissipation on t he on... more As CMOS VLSI integration continues with shrinking feature size, the energy dissipation on t he on-chip data buses and long interconnects becoming a bottle neck for high performance integrated circuits. This energy dissipation is due to increase in inter-wire capacitance. This capacitance on on-chip data buses and long interconnects plays an important role in the reliability and performance of the system. These on-chip data buses consumes major portion of wiring energy. Hence this energy dissipation can be reduced by encoding the data on the data bus. Hence transition energy reduction data bus encoding scheme is proposed which can reduce the energy dissipation on on -chip data buses. The proposed technique can able to reduce the energy dissipation by 42% to 47% for 8-bit, 16-bit, 32-bit and 64-bit data buses compare with unencoded data and 1% to 26% more compare with other existing techniques.

Energy dissipation of interconnects is becoming a bottle neck for high performance integrated cir... more Energy dissipation of interconnects is becoming a bottle neck for high performance integrated circuits. This energy dissipation is due to increase in inter-wire capacitance. As CMOS VLSI integration continues with shrinking feature size, the energy dissipation on the on-chip data buses and long capacitance also increases. This capacitance on on-chip data buses and long interconnects plays an important role in the reliability and performance of the system. These onchip data buses consumes major portion of wiring energy. To increase the reliability and performance of the system it is necessary to reduce the energy dissipation on the data bus. Hence transition energy reduction data bus encoding scheme is proposed which can reduce the energy dissipation on on-chip data buses. The proposed technique can able to reduce the energy dissipation by 32% to 40% for 12-bit, 21-bit, 38-bit and 71-bit data buses compare with unencoded data and 1% to 31% more compare with other existing techniques.

A.P. PG Student RGMCET, Nandyal, A.P.

A.P PG student RGMCET, Nandyal, A.P.