Eby Friedman | University of Rochester (original) (raw)

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Papers by Eby Friedman

Research paper thumbnail of Ac-Dimm

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Research paper thumbnail of Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing

IEEE Micro, Sep 1, 2015

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Research paper thumbnail of Power noise in 14, 10, and 7 nm FinFET CMOS technologies

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Research paper thumbnail of Arithmetic encoding for memristive multi-bit storage

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Research paper thumbnail of On-Chip Power Delivery and Management

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Research paper thumbnail of Superconductive Logic Using 2ϕ—Josephson Junctions With Half Flux Quantum Pulses

IEEE Transactions on Circuits and Systems II: Express Briefs, 2022

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Research paper thumbnail of MAGIC—Memristor-Aided Logic

IEEE Transactions on Circuits and Systems Ii-express Briefs, Nov 1, 2014

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Research paper thumbnail of Nanosession: Logic Devices and Circuit Design

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Research paper thumbnail of 2T–1R STT-MRAM memory cells for enhanced on/off current ratio

Microelectronics Journal, 2014

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Research paper thumbnail of Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020

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Research paper thumbnail of Global interconnects in VLSI complexity single flux quantum systems

Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop, 2020

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Research paper thumbnail of Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019

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Research paper thumbnail of Inductive coupling effects in large TSV arrays

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015

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Research paper thumbnail of A unified design methodology for CMOS tapered buffers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

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Research paper thumbnail of Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical Interconnect

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Research paper thumbnail of Power Delivery Exploration Methodology based on Constrained Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

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Research paper thumbnail of Power Delivery Exploration Methodology based on Constrained Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

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Research paper thumbnail of A bulk-driven CMOS OTA with 68 dB DC gain

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.

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Research paper thumbnail of Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

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Research paper thumbnail of Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits -- Vertical integration is a novel communications paradigm where interconnect design is a primary focus

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achiev... more Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manu-facturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient tomanage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added com-plexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated

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Research paper thumbnail of Ac-Dimm

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Research paper thumbnail of Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing

IEEE Micro, Sep 1, 2015

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Research paper thumbnail of Power noise in 14, 10, and 7 nm FinFET CMOS technologies

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Arithmetic encoding for memristive multi-bit storage

Bookmarks Related papers MentionsView impact

Research paper thumbnail of On-Chip Power Delivery and Management

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Superconductive Logic Using 2ϕ—Josephson Junctions With Half Flux Quantum Pulses

IEEE Transactions on Circuits and Systems II: Express Briefs, 2022

Bookmarks Related papers MentionsView impact

Research paper thumbnail of MAGIC—Memristor-Aided Logic

IEEE Transactions on Circuits and Systems Ii-express Briefs, Nov 1, 2014

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Research paper thumbnail of Nanosession: Logic Devices and Circuit Design

Bookmarks Related papers MentionsView impact

Research paper thumbnail of 2T–1R STT-MRAM memory cells for enhanced on/off current ratio

Microelectronics Journal, 2014

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020

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Research paper thumbnail of Global interconnects in VLSI complexity single flux quantum systems

Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop, 2020

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019

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Research paper thumbnail of Inductive coupling effects in large TSV arrays

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015

Bookmarks Related papers MentionsView impact

Research paper thumbnail of A unified design methodology for CMOS tapered buffers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

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Research paper thumbnail of Initial Results of Prototyping a 3-D Integrated Intra-Chip Free-Space Optical Interconnect

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Power Delivery Exploration Methodology based on Constrained Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Power Delivery Exploration Methodology based on Constrained Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019

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Research paper thumbnail of A bulk-driven CMOS OTA with 68 dB DC gain

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits -- Vertical integration is a novel communications paradigm where interconnect design is a primary focus

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achiev... more Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manu-facturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient tomanage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added com-plexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated

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