Pramod Aswale | Sandip Foundation (original) (raw)
Papers by Pramod Aswale
Social Science Research Network, 2020
This paper focuses on Real time Invisibility of object. That means how object can be made invisib... more This paper focuses on Real time Invisibility of object. That means how object can be made invisible or get disappear. Main Objective of this project is to design, develop and demonstrate a state of art technology invisibility (Cloaking) by employing combination of various techniques and components such as electro – optical sensors, signal polarization, spectrum distortion, exploitation of thermal properties of technology and nano technology.<br><br>Concept is that whatever object that we can see in this universe have some symmetrical internal structure because of which it reflects object and hence we can see it. Therefore we need to design material which has internal structure differ from object/ material which exists in universe. Such kind of material is known as metamaterial.<br><br>Metamterial can be designed by mixing two different material in which one material is insulator.<br><br>In this paper, after performing several experiments we have proposed two ways through which invisibility can be achieved: 1. By using metamaterials, 2. By Lubor lenses. <br><br>This project has following applications:<br><br>1. In military field: to make our military bases, equipments etc invisible,<br><br>2. In medical field: to perform operation without cutting the body parts.<br>
Multipliers being the key components of various applications and the throughput of applications d... more Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing (DSP) blocks and Multiplier and accumulate units(MAC). Vedic Multiplier has become highly popular as a faster method for computation and analysis. So that the latency of conventional multiplier can be reduced .The design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) is implemented to improve the performance. The use of Vedic Mathematics is made because it reduces the steps and time consumed in computation of partial products. In the proposed method, this process is done in a single step. The only two vedic mathematics sutras“Urdhva Tiryagbhyam" and “Nikhilum" are used for multiplication. “Urdhva Tiryagbhyam" is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. We are g...
Information and Communication Technology for Intelligent Systems
Internet of Things is a fast-emerging technology, flourishing in many trends, like making smart h... more Internet of Things is a fast-emerging technology, flourishing in many trends, like making smart homes, industries, health care, and many more. From a technological outlook, it allows the expansion of fresh protocols and circumstances, as the existing protocols cannot handle the increasing amount of devices connected and the data being transferred. Internet of Things (IoT) can be defined as the prevalent and worldwide network which helps in delivering a system for checking and regulating the physical world with the help of protocols and IOT sensors. The IOT enforces that all objects, like smartphones, smart watches, and similar gadgets insert with the other components as in sensors linked to a common network so any individual may communicate with any resource at any time when required, by using a source that is known in the network. This paper confers a rational survey of architecture, protocols, applications, and challenges in context of Internet of Things.
International Journal of Computer Applications, Dec 15, 2016
Multipliers being the key components of various applications and the throughput of applications d... more Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing blocks and Multiplier and accumulate units. Vedic Multiplier has become highly popular as a faster method for computation and analysis.So that the latency of conventional multiplier can be reduced. Here the vedic mathematic Sutra-'Urdhva Tiryagbhyam' and Nikhilum are used for efficient multiplication. The main parameters for improvement are speed, delay, hardware complexity. From this review, the conclusion regarding how well a challenge has been solved, and recognize prospective research areas that require auxiliary effort.
Nowadays application specific soft processor cores are gaining importance for FPGA based embedded... more Nowadays application specific soft processor cores are gaining importance for FPGA based embedded application in which user can configure the processor as per requirement. The architectural simplicity of ARM processors makes them suitable for low power applications. Hardware description languages (HDLs) are commonly used to construct hardware system. FPGA provides reconfigurable platform, so reuse of the design is a common practice to improve the productivity nowadays. In this paper the data processing instructions of ARM processor are implemented using Very high speed integrated circuit Hardware Description Language (VHDL) language and verified by applying test bench on Xilinx's Spartan III based FPGA.
High speed, low power consumption are key requirement to any VLSI design. The power efficient mul... more High speed, low power consumption are key requirement to any VLSI design. The power efficient multipliers play an important role. This paper presents an efficient implementation of a high speed, low power multiplier using shift and adds methods of Baugh Wooely Multiplier. This study presented the design and implementation of Baugh wooely multipliers using Cadence (Encounter) RTL Complier. In this work, Modified Baugh Wooely is having least area, power and delay. The Modified Baugh wooley architecture is 109X faster than Conventional array multiplier and 102X faster than conventional Baugh Wooley. The operating frequency of 5 x 5 Design Modified Baugh Wooley multiplier is 160MHz. The Selection of Multiplier should be done depending on performance measure and application nature.
International Research Journal on Advanced Science Hub
Social Science Research Network, 2020
This paper focuses on Real time Invisibility of object. That means how object can be made invisib... more This paper focuses on Real time Invisibility of object. That means how object can be made invisible or get disappear. Main Objective of this project is to design, develop and demonstrate a state of art technology invisibility (Cloaking) by employing combination of various techniques and components such as electro – optical sensors, signal polarization, spectrum distortion, exploitation of thermal properties of technology and nano technology.<br><br>Concept is that whatever object that we can see in this universe have some symmetrical internal structure because of which it reflects object and hence we can see it. Therefore we need to design material which has internal structure differ from object/ material which exists in universe. Such kind of material is known as metamaterial.<br><br>Metamterial can be designed by mixing two different material in which one material is insulator.<br><br>In this paper, after performing several experiments we have proposed two ways through which invisibility can be achieved: 1. By using metamaterials, 2. By Lubor lenses. <br><br>This project has following applications:<br><br>1. In military field: to make our military bases, equipments etc invisible,<br><br>2. In medical field: to perform operation without cutting the body parts.<br>
Multipliers being the key components of various applications and the throughput of applications d... more Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing (DSP) blocks and Multiplier and accumulate units(MAC). Vedic Multiplier has become highly popular as a faster method for computation and analysis. So that the latency of conventional multiplier can be reduced .The design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) is implemented to improve the performance. The use of Vedic Mathematics is made because it reduces the steps and time consumed in computation of partial products. In the proposed method, this process is done in a single step. The only two vedic mathematics sutras“Urdhva Tiryagbhyam" and “Nikhilum" are used for multiplication. “Urdhva Tiryagbhyam" is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. We are g...
Information and Communication Technology for Intelligent Systems
Internet of Things is a fast-emerging technology, flourishing in many trends, like making smart h... more Internet of Things is a fast-emerging technology, flourishing in many trends, like making smart homes, industries, health care, and many more. From a technological outlook, it allows the expansion of fresh protocols and circumstances, as the existing protocols cannot handle the increasing amount of devices connected and the data being transferred. Internet of Things (IoT) can be defined as the prevalent and worldwide network which helps in delivering a system for checking and regulating the physical world with the help of protocols and IOT sensors. The IOT enforces that all objects, like smartphones, smart watches, and similar gadgets insert with the other components as in sensors linked to a common network so any individual may communicate with any resource at any time when required, by using a source that is known in the network. This paper confers a rational survey of architecture, protocols, applications, and challenges in context of Internet of Things.
International Journal of Computer Applications, Dec 15, 2016
Multipliers being the key components of various applications and the throughput of applications d... more Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing blocks and Multiplier and accumulate units. Vedic Multiplier has become highly popular as a faster method for computation and analysis.So that the latency of conventional multiplier can be reduced. Here the vedic mathematic Sutra-'Urdhva Tiryagbhyam' and Nikhilum are used for efficient multiplication. The main parameters for improvement are speed, delay, hardware complexity. From this review, the conclusion regarding how well a challenge has been solved, and recognize prospective research areas that require auxiliary effort.
Nowadays application specific soft processor cores are gaining importance for FPGA based embedded... more Nowadays application specific soft processor cores are gaining importance for FPGA based embedded application in which user can configure the processor as per requirement. The architectural simplicity of ARM processors makes them suitable for low power applications. Hardware description languages (HDLs) are commonly used to construct hardware system. FPGA provides reconfigurable platform, so reuse of the design is a common practice to improve the productivity nowadays. In this paper the data processing instructions of ARM processor are implemented using Very high speed integrated circuit Hardware Description Language (VHDL) language and verified by applying test bench on Xilinx's Spartan III based FPGA.
High speed, low power consumption are key requirement to any VLSI design. The power efficient mul... more High speed, low power consumption are key requirement to any VLSI design. The power efficient multipliers play an important role. This paper presents an efficient implementation of a high speed, low power multiplier using shift and adds methods of Baugh Wooely Multiplier. This study presented the design and implementation of Baugh wooely multipliers using Cadence (Encounter) RTL Complier. In this work, Modified Baugh Wooely is having least area, power and delay. The Modified Baugh wooley architecture is 109X faster than Conventional array multiplier and 102X faster than conventional Baugh Wooley. The operating frequency of 5 x 5 Design Modified Baugh Wooley multiplier is 160MHz. The Selection of Multiplier should be done depending on performance measure and application nature.
International Research Journal on Advanced Science Hub