Yajuan He | University of Electronic Science and Technology of China (original) (raw)

Papers by Yajuan He

Research paper thumbnail of Low power implementation of FFT/IFFT processor for IEEE 802.11a wireless LAN transceiver

Research paper thumbnail of A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

IEEE Transactions on Circuits and Systems I-regular Papers, 2008

Research paper thumbnail of A novel covalent redundant binary Booth encoder

The benefit of high radix Booth encoders in reducing the number of partial products in fast multi... more The benefit of high radix Booth encoders in reducing the number of partial products in fast multipliers has been hampered by the complexity of generating the hard multiples. The use of redundant binary (RB) Booth encoder can overcome this problem and avoid the error compensation vector but at the cost of doubling the number of RB partial products. This paper presents a novel covalent RB Booth encoder to generate a compound RB partial product from two adjacent Booth encoded digits. The new encoder fully exploits the characteristics of Booth encoded numbers to restore the effective partial product reduction rate of RB Booth encoder while maintaining the simplicity of hard multiple generators and eliminating the constant correction vector. A legitimate comparison on an 8×8-bit RB multiplier prototype shows that the multiplier constructed with our proposed Booth encoder consumes lower power and computes faster than those with the normal binary and redundant binary Booth encoders. 0-7803-8834-8/05/$20.00 ©2005 IEEE.

Research paper thumbnail of An alternative scheme of redundant binary multiplier

ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that i... more ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.

Research paper thumbnail of A New Redundant Binary Booth Encoding for Fast Bit Multiplier Design

IEEE Transactions on Circuits and Systems I-regular Papers, 2009

Research paper thumbnail of A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier

In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter f... more In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter for RB multiplication is presented. A new conversion algorithm is proposed to fully exploit the redundancy of RB encoding for a VLSI efficient implementation. The hierarchical linear expansion of the carry equation creates a regular multi-level parallel structure which is well suited for implementation with a logarithmic depth hybrid carry-lookahead/carry-select (CLA/ CSL) adder. A special add-one circuit is also incorporated into the CSL circuit to further reduce its logic complexity. A 64-bit reverse converter is designed using TSMC 0.18 mum CMOS Technology. Pre-layout HSPICE simulation of the proposed design shows that it is capable of completing a 64-bit conversion in 761 ps and dissipates merely 0.34 mW at a data rate of 100MHz and a supply voltage of 1.8V

Research paper thumbnail of An area efficient 64-bit square root carry-select adder for low power applications

The carry-select method has deemed to be a good compromise between cost and performance in carry ... more The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 μm CMOS technology.

Research paper thumbnail of A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

IEEE Transactions on Circuits and Systems I-regular Papers, 2008

Research paper thumbnail of A novel covalent redundant binary Booth encoder

The benefit of high radix Booth encoders in reducing the number of partial products in fast multi... more The benefit of high radix Booth encoders in reducing the number of partial products in fast multipliers has been hampered by the complexity of generating the hard multiples. The use of redundant binary (RB) Booth encoder can overcome this problem and avoid the error compensation vector but at the cost of doubling the number of RB partial products. This paper presents a novel covalent RB Booth encoder to generate a compound RB partial product from two adjacent Booth encoded digits. The new encoder fully exploits the characteristics of Booth encoded numbers to restore the effective partial product reduction rate of RB Booth encoder while maintaining the simplicity of hard multiple generators and eliminating the constant correction vector. A legitimate comparison on an 8×8-bit RB multiplier prototype shows that the multiplier constructed with our proposed Booth encoder consumes lower power and computes faster than those with the normal binary and redundant binary Booth encoders. 0-7803-8834-8/05/$20.00 ©2005 IEEE.

Research paper thumbnail of An alternative scheme of redundant binary multiplier

ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that i... more ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.

Research paper thumbnail of A New Redundant Binary Booth Encoding for Fast Bit Multiplier Design

IEEE Transactions on Circuits and Systems I-regular Papers, 2009

Research paper thumbnail of A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier

In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter f... more In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter for RB multiplication is presented. A new conversion algorithm is proposed to fully exploit the redundancy of RB encoding for a VLSI efficient implementation. The hierarchical linear expansion of the carry equation creates a regular multi-level parallel structure which is well suited for implementation with a logarithmic depth hybrid carry-lookahead/carry-select (CLA/ CSL) adder. A special add-one circuit is also incorporated into the CSL circuit to further reduce its logic complexity. A 64-bit reverse converter is designed using TSMC 0.18 mum CMOS Technology. Pre-layout HSPICE simulation of the proposed design shows that it is capable of completing a 64-bit conversion in 761 ps and dissipates merely 0.34 mW at a data rate of 100MHz and a supply voltage of 1.8V

Research paper thumbnail of An area efficient 64-bit square root carry-select adder for low power applications

The carry-select method has deemed to be a good compromise between cost and performance in carry ... more The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 μm CMOS technology.

Research paper thumbnail of Low power implementation of FFT/IFFT processor for IEEE 802.11a wireless LAN transceiver

Research paper thumbnail of A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

IEEE Transactions on Circuits and Systems I-regular Papers, 2008

Research paper thumbnail of A novel covalent redundant binary Booth encoder

The benefit of high radix Booth encoders in reducing the number of partial products in fast multi... more The benefit of high radix Booth encoders in reducing the number of partial products in fast multipliers has been hampered by the complexity of generating the hard multiples. The use of redundant binary (RB) Booth encoder can overcome this problem and avoid the error compensation vector but at the cost of doubling the number of RB partial products. This paper presents a novel covalent RB Booth encoder to generate a compound RB partial product from two adjacent Booth encoded digits. The new encoder fully exploits the characteristics of Booth encoded numbers to restore the effective partial product reduction rate of RB Booth encoder while maintaining the simplicity of hard multiple generators and eliminating the constant correction vector. A legitimate comparison on an 8×8-bit RB multiplier prototype shows that the multiplier constructed with our proposed Booth encoder consumes lower power and computes faster than those with the normal binary and redundant binary Booth encoders. 0-7803-8834-8/05/$20.00 ©2005 IEEE.

Research paper thumbnail of An alternative scheme of redundant binary multiplier

ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that i... more ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.

Research paper thumbnail of A New Redundant Binary Booth Encoding for Fast Bit Multiplier Design

IEEE Transactions on Circuits and Systems I-regular Papers, 2009

Research paper thumbnail of A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier

In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter f... more In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter for RB multiplication is presented. A new conversion algorithm is proposed to fully exploit the redundancy of RB encoding for a VLSI efficient implementation. The hierarchical linear expansion of the carry equation creates a regular multi-level parallel structure which is well suited for implementation with a logarithmic depth hybrid carry-lookahead/carry-select (CLA/ CSL) adder. A special add-one circuit is also incorporated into the CSL circuit to further reduce its logic complexity. A 64-bit reverse converter is designed using TSMC 0.18 mum CMOS Technology. Pre-layout HSPICE simulation of the proposed design shows that it is capable of completing a 64-bit conversion in 761 ps and dissipates merely 0.34 mW at a data rate of 100MHz and a supply voltage of 1.8V

Research paper thumbnail of An area efficient 64-bit square root carry-select adder for low power applications

The carry-select method has deemed to be a good compromise between cost and performance in carry ... more The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 μm CMOS technology.

Research paper thumbnail of A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

IEEE Transactions on Circuits and Systems I-regular Papers, 2008

Research paper thumbnail of A novel covalent redundant binary Booth encoder

The benefit of high radix Booth encoders in reducing the number of partial products in fast multi... more The benefit of high radix Booth encoders in reducing the number of partial products in fast multipliers has been hampered by the complexity of generating the hard multiples. The use of redundant binary (RB) Booth encoder can overcome this problem and avoid the error compensation vector but at the cost of doubling the number of RB partial products. This paper presents a novel covalent RB Booth encoder to generate a compound RB partial product from two adjacent Booth encoded digits. The new encoder fully exploits the characteristics of Booth encoded numbers to restore the effective partial product reduction rate of RB Booth encoder while maintaining the simplicity of hard multiple generators and eliminating the constant correction vector. A legitimate comparison on an 8×8-bit RB multiplier prototype shows that the multiplier constructed with our proposed Booth encoder consumes lower power and computes faster than those with the normal binary and redundant binary Booth encoders. 0-7803-8834-8/05/$20.00 ©2005 IEEE.

Research paper thumbnail of An alternative scheme of redundant binary multiplier

ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that i... more ABSTRACT This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant number representation called the non-carry-propagation (NCP) format to avoid carry propagation. The preliminary theoretical assessments and simulation result show that this multiplier possesses certain revelatory features that make it a potential alternative approach to conventional redundant binary multiplier. The characteristics of NCP number and the structure of NCP adders array are analyzed. A new reverse converter was also proposed to simplify the converter circuit that converts the final redundant binary number into the corresponding 2's complement number. A recommended gate-level implementation of the multiplier based on this new architecture is also presented.

Research paper thumbnail of A New Redundant Binary Booth Encoding for Fast Bit Multiplier Design

IEEE Transactions on Circuits and Systems I-regular Papers, 2009

Research paper thumbnail of A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier

In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter f... more In this paper, a power-delay efficient redundant binary (RB) to 2's complement number converter for RB multiplication is presented. A new conversion algorithm is proposed to fully exploit the redundancy of RB encoding for a VLSI efficient implementation. The hierarchical linear expansion of the carry equation creates a regular multi-level parallel structure which is well suited for implementation with a logarithmic depth hybrid carry-lookahead/carry-select (CLA/ CSL) adder. A special add-one circuit is also incorporated into the CSL circuit to further reduce its logic complexity. A 64-bit reverse converter is designed using TSMC 0.18 mum CMOS Technology. Pre-layout HSPICE simulation of the proposed design shows that it is capable of completing a 64-bit conversion in 761 ps and dissipates merely 0.34 mW at a data rate of 100MHz and a supply voltage of 1.8V

Research paper thumbnail of An area efficient 64-bit square root carry-select adder for low power applications

The carry-select method has deemed to be a good compromise between cost and performance in carry ... more The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 μm CMOS technology.