Ricardo Augusto da Luz Reis | Universidade Federal do Rio Grande do Sul (original) (raw)

Papers by Ricardo Augusto da Luz Reis

VLSI-SoC series of conferences started in 1981 and this chapter presents a little bit of its hist... more VLSI-SoC series of conferences started in 1981 and this chapter presents a little bit of its history. Since the beginning, the conference moves around the world, showing recent works in the field of VLSI and Systems-on-Chip design and design automation. The contents of books related to the set of event editions is in some way a witness of the extraordinary evolution of the field in these almost 4 decades.

Revista de Informática Teórica e Aplicada, 2004

The work described in this paper aims to allow the flexible distribution of resources and tools s... more The work described in this paper aims to allow the flexible distribution of resources and tools supporting the design of integrated systems and considers specifically the need for collaborative interaction among designers. Particular emphasis was given to issues which were only marginally considered in previous approaches, such as the abstraction of the distribution of design automation resources over the network, the consistency control on both synchronous and asynchronous interaction among designers and the support for extensible design data models.

Analog Integrated Circuits and Signal Processing, 2016

to promote the research carried out by young professionals, M.Sc. and Ph.D. students, ''IEEE ICEC... more to promote the research carried out by young professionals, M.Sc. and Ph.D. students, ''IEEE ICECS 2014 has organized a Women in CAS/ Young Professionals/M.Sc./Ph.D. students Forum. The two first papers presented in this special issue have been selected from the Forum.

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014

Electromigration (EM) is a significant problem in integrated circuits and can seriously damage in... more Electromigration (EM) is a significant problem in integrated circuits and can seriously damage interconnect wires and vias, reducing the circuit's lifetime. In this paper we are testing the EM effects on 6 different metal layers for different wire lengths. The layouts are constructed considering the 45nm technology and scaled to 22nm technology. We are testing the EM effects considering three different wire lengths, 100µm, 200µm and 300µm in 22nm technology. The delay is also analyzed and it increases when the wire length increases and decreases for a higher metal layer.

IFIP International Federation for Information Processing

The main challenge to set up an computer environment for microelectronics education (design or CA... more The main challenge to set up an computer environment for microelectronics education (design or CAD) is to have a resourceful and specific framework and to made a consortium to fill this framework with tools that really use the advantages and facilities that a computer provides. Comparing to printed books, any figure should be transformed in a tool that could simulate the problem related. It also should allow the student interaction with. The learning flow of a computer-based course should also be different from traditional learning flows. The paper shortly extends this point proposing a new learning flow.

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005.

Consistency Control in Data-driven Design Automation Environments Leandro Soares Indrusiak1, Tudo... more Consistency Control in Data-driven Design Automation Environments Leandro Soares Indrusiak1, Tudor Murgan1, Manfred Glesner1, Ricardo Reis2 1 Microelectronic Systems Institute, Technische Universitat Darmstadt, Germany 2 Informatics ... Reading: Addison Wesley, 1995. ...

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 2013

The Computer Journal, 2006

Reis-Google Scholar Citations SRAM memory cells, SRAM-based FPGAs are also sensitive to radiation... more Reis-Google Scholar Citations SRAM memory cells, SRAM-based FPGAs are also sensitive to radiation and. tolerance technique for transient and permanent faults in SRAM-based. FPGAs. Fault-Tolerance Techniques for SRAM-Based FPGAs .-Amazon.com Fault-Tolerance Techniques for Sram-Based FPGAs Facebook Fault-tolerance Techniques for Sram-based Fpgas-Kastensmidt. This book reviews fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs), outlining many methods for designing fault tolerance. Fault Tolerance Implementation within SRAM Based FPGA Designs. This article presents a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison Fault-Tolerance Techniques for Sram-Based FPGAs This book reviews fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs), outlining many methods for designing fault tolerance. Designing Fault-Tolerant Techniques for SRAM-Based FPGAs Fault-tolerance Techniques for Sram-based Fpgas-Kastensmidt, Fernanda Lima/ Ca in Books, Comics & Magazines, Non-Fiction eBay. 6 Dec 2004. FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. We present a fault Fault-Tolerance Techniques for SRAM-Based FPGAs-Fernanda. 5 Nov 2013. niques of fault-tolerance for SRAM based FPGAs. Section 3 presents the permanent effect and fault tolerance techniques must correct it. Designing Fault-Tolerant Techniques for SRAM-Based FPGAs Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic. Morihiro Kuga , Masahiro Iida , Toshinori Sueyoshi, Fault recovery technique for Fault-Tolerance Techniques for Sram-Based FPGAs » Vector. Fault tolerance is the ability of a system to operate normally given the presence of. SRAM-based FPGAs has made it possible to incorporate fault tolerance into Autonomous Fault-Tolerant Systems onto SRAM-based FPGA. methods and fault tolerance schemes specifically for. methods in FPGAs over the past 15 years. .. J. Kelly et al, "Defect tolerant SRAM based FPGAs", Int. Fault Tolerant Techniques for Reconfigurable Devices: a brief Survey This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications Fault-Tolerance Techniques for SRAM-Based FPGAs Fernanda. Amazon.in-Buy Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) book online at best prices in India on Amazon.in.

2020 28th European Signal Processing Conference (EUSIPCO), 2021

This work proposes a hardware architecture for fractional-pixel interpolation filter defined in t... more This work proposes a hardware architecture for fractional-pixel interpolation filter defined in the royalty-free AV1 video coding standard. Analysis conducted in this work shows that the AV1 Regular family of filters has the highest usage especially when considering high resolution videos. The proposed architecture implements the 15 interpolation filters of the AV1 Regular family and is capable to interpolate videos of up to 8K video resolution at 120 fps. The proposed architecture achieves the highest throughput compared to related works.

Integration, 2020

In advanced technology nodes, IC implementation faces increasing design complexity as well as eve... more In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies it would be very valuable to better predict final placement of the gate-level netlist: this would enable more accurate early assessment of performance, congestion and floorplan viability in the SOC floorplanning/RTL planning stages of design. In this work, we study a new criterion for the classic challenge of VLSI netlist clustering: how well netlist clusters "stay together" through final implementation. We propose the use of several evaluators of this criterion. We also explore the use of modularity-driven clustering to identify natural clusters in a given graph without the tuning of parameters and size balance constraints typically required by VLSI CAD partitioning methods. We find that the netlist hypergraph-to-graph mapping can significantly affect quality of results, and we experimentally identify an effective recipe for weighting that also comprehends topological proximity to I/Os. Further, we empirically demonstrate that modularity-based clustering achieves better correlation to actual netlist placements than traditional VLSI CAD methods (our method is also 2× faster than use of hMetis for our largest testcases). Finally, we propose a flow with fast "blob placement" of clusters. The "blob placement" is used as a seed for a global placement tool that performs placement of the flat netlist. With this flow we achieve 20% speedup on the placement of a netlist with 4.9 M instances with less than 3% difference in routed wirelength.

Revista de Informática Teórica e Aplicada, 2012

Este trabalho explora métodos para realizar o posicionamento de um tipo particular de circuitos V... more Este trabalho explora métodos para realizar o posicionamento de um tipo particular de circuitos VLSI conhecido como circuito 3D (três dimensões). Este artigo aborda o problema de posicionamento 3D considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um fluxo completo de posicionamento, iniciando pelo tratamento de pinos de entrada e saída (E/S), seguindo com posicionamento global, posicionamento detalhado e posicionamento das 3D-Vias. A primeira etapa busca a distribuição dos pinos de E/S de maneira equilibrada objetivando auxiliar o posicionamento para obter uma quantidade reduzida de 3D-Vias. O mecanismo de posicionamento global baseado no algorítmo de Quadratic Placement considera informações fornecidas pela tecnologia de fabricação e requisito de espaçamento de 3D-Vias para reduzir o comprimento das conexões e equilibrar a distribuição das células em 3D. Conexões críticas podem ser tratadas através da inserção de redes artificiais que auxiliam a evitar que 3D-Vias sejam usadas em sua implementação. Finalmente, as 3D-Vias são posicionadas por um algorítmo rápido baseado na legalização Tetris. O sistema completo reforça os potenciais benefícios dos circuitos 3D para reduzir o comprimento das conexões e apresenta algorítmos eficientes projetados para circuitos 3D que podem ser incorporados em novas ferramentas de CAD (Computer Aided Design).

IFIP Advances in Information and Communication Technology, 2019

The Internet of Things (IoT) demands new challenges in the design of computing and electronics co... more The Internet of Things (IoT) demands new challenges in the design of computing and electronics components. One of the challenges is the power reduction of this expanding network of connected devices, where the majority is permanently connected. In a large set of applications, another significant issue is reliability, especially on critical areas as health and transport. This paper shows an overview of design strategies that we have developed to reduce power consumption and to increase reliability in circuits that are components of the IoT, as the reduction of the number of transistors in IoT devices, using optimisation techniques and the physical design of circuits tolerant to radiation effects.

16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.

True critical path identification is still an issue of relevant importance in the physical design... more True critical path identification is still an issue of relevant importance in the physical design of CMOS VLSI circuits. Although delay enumeration-based timing analysis methods are independent of the number of long false paths, they are not able to identify the true critical paths of a combinational block. Hence, path enumeration-based timing analysis must be used. In this paper we present a new heuristic for ordering the objectives that need to be satisfied for declaring a path as sensitizable. The new heuristic is compared to the commonly used one, which relies on following the logical depth of the circuit. The practical results showed that the proposed heuristic tends to provide better results.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mec... more Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216)

Most of path enumeration-based timing analysis tools use a single delay per gate for path delay c... more Most of path enumeration-based timing analysis tools use a single delay per gate for path delay calculation. However, the timing analysis of current submicronic designs demands more accurate delay calculation methods, which can improve path enumeration accuracy and especially, critical delay estimation accuracy. This article presents modifications to the classical bestfirst procedure proposed by Yen and collaborators [1] in order to consider a pair of delays per gate. The increase in the accuracy of path delay calculation is evaluated by running both the original and the improved path delay calculation methods on the ISCASÕ85 circuits.

IFIP – The International Federation for Information Processing, 2009

Statistical process variations are a critical issue for circuit design strategies to ensure high ... more Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we investigate the variability of flip-flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ~1ps is used to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to-die variations of hold time violations are measured in various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12-16%. Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm. Normality tests to check if the variability follows a normal Gaussian distribution are also presented.

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design Chip on the Dunes - SBCCI '09, 2009

ABSTRACT Statistical process variations are a critical issue to define circuit design strategies ... more ABSTRACT Statistical process variations are a critical issue to define circuit design strategies to ensure high yield in sub-100nm technologies. This work focuses on hold time violation probabilities in sub-100 nm technologies. The variability in flip-flop race immunity and clock skew is evaluated, and a methodology for the estimation of hold time violation probability is developed. This violation probability is analyzed at different technologies, flip-flop strength, supply voltage and padding. Then three different methods to protect against hold time violations are evaluated: Vdd reduction, race immunity increase, and padding. Each of them has different advantages and drawbacks that must be taken into account. It is shown that at design time the most effective method is padding. An algorithm to automatically insert padding in digital circuits considering process variability is presented. The proposed algorithm will be evaluated compared to other ways to protect against violations.

2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012

This paper presents two adder compressors architectures addressing high-speed and low power. Adde... more This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper are combined optimizations at logic, electrical and physical level. At the logic level, the circuit is optimized by using multiplexers instead of XOR gates to reduce delay, power and area. At the electrical level, this work presents an architecture that generate the XOR and XNOR signals simultaneously, this reduce internal glitches hence dynamic power as well. And finally at the physical level, and automatic layout generation tool (ASTRAN) is used to make the adder compressors layouts. This tool has proved to reduce power consumption and delay due to the smaller input capacitances of the complex gates generated compared to manual-designed layouts.