M. Valenza | Université de Montpellier (original) (raw)

Papers by M. Valenza

30th European Solid-State Device Research Conference, 2000

ABSTRACT First Page of the Article

Channel noise of MOS integrated tetrodes is investigated versus frequency and bias. The behavior ... more Channel noise of MOS integrated tetrodes is investigated versus frequency and bias. The behavior is analyzed in the four operation modes taking into account the variations of the small signal parameters. Voltage-gain and noise figure are simultaneously measured. The two inputs are investigated. Experimental results and their interpretations lead to the bias range giving the best compromise between high voltage-gain and low noise figure.

2011 - 14th International Symposium on Electrets, 2011

ABSTRACT In this work, the authors demonstrate that the meta-stable DRAM (MSDRAM) can achieve bet... more ABSTRACT In this work, the authors demonstrate that the meta-stable DRAM (MSDRAM) can achieve better performances regarding to the sensing margin compared to programming methods like impact ionization and forward biased junctions. This improvement results mainly from the low current level at 0-state. Indeed, the MSDRAM uses gate capacitive coupling method which allows to reach zero current level. Finally, the band-to-band tunneling used to program the 1-state strongly reduces the power consumption and improves the device reliability. These promising results promote the meta-stable dip (MSD) programming mechanism as a viable solution for low power single-transistor DRAM memories.

2011 21st International Conference on Noise and Fluctuations, 2011

This paper presents low-frequency noise in Si 0.75 Ge 0.25 and Si 0.65 Ge 0.35 p-and n-channel st... more This paper presents low-frequency noise in Si 0.75 Ge 0.25 and Si 0.65 Ge 0.35 p-and n-channel strained Germanium on Insulator (SGOI) MOSFETs with 15nm thick substrates and with TiN/HfO 2 /SiO 2 gate stacks, obtained using the enrichment technique. In strong inversion, front and back interface current noise in PMOSFET devices is described using the ∆ ∆ ∆ ∆N model, whereas NMOSFET noise is described using the ∆ ∆ ∆ ∆N-∆ ∆ ∆ ∆µ model, with a ten-fold increase in noise in some cases. In weak inversion, the noise behavior deviates from these standard models and may be described by noise coupling between the two interfaces. For both types of device, the extracted densities are approximately the same, with no significant impact from the variation of the Ge content.

Noise in Devices and Circuits, 2003

Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE,... more Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE, HSPICE and recently BSIM3v3 noise model. The aim of this contribution is to show the limitation for each of these implementations by comparing noise simulations to noise measurement data.

Noise in Physical Systems and 1/f Fluctuations - ICNF 2001 - Proceedings of the 16th International Conference, 2001

Microelectronics Reliability, 2007

ABSTRACT This paper presents the electrical characterization of thick and thin SiO2 oxynitride pe... more ABSTRACT This paper presents the electrical characterization of thick and thin SiO2 oxynitride performed by thermal and plasma nitridation processes. The impact of the nitridation technique is investigated using random telegraph signal (RTS) noise analysis. The variation of the gate oxide trap characteristics is determined with respect to the nitridation technique. Significant properties of traps are also pointed out. Main trap parameters, such as their depth with respect to the interface, nature, capture and emission times are extracted. These results illustrate the potential of RTS noise investigation for gate oxide characterizations.

Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is ... more Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is demonstrated that experimental fully depleted devices can operate in the 'back-interface inversion' regime even at VG2 grounded. As a result, two threshold voltages appear in the transistors, with an experimental difference of threshold voltages up to several hundreds mV for planar FDSOI devices. As

Gate and drain current /f noise parameters have been extracted in p-metal-oxide-semiconductor tra... more Gate and drain current /f noise parameters have been extracted in p-metal-oxide-semiconductor transistors processed with two nitridation techniques (RTN or DPN). The drain noise magnitude allows extraction of the slow oxide trap density Nt(EF) in the range of 3 1017 eV-1 cm-3. We don't observe any improvement of the /f noise performance for DPN devices, which is in opposition with the trends observed on thicker oxides. 1/f gate current noise has been also investigated for these devices, and similar results have been obtained concerning the /f noise levels. The benefit in changing process for thick oxide doesn't hold any longer in term on /f noise performance with an equivalent oxide thickness of 1.2 nm.

Solid-State Electronics, 2012

This paper presents low-frequency noise in cSi 0.75 Ge 0.25 and cSi 0.65 Ge 0.35 p-and n-channel ... more This paper presents low-frequency noise in cSi 0.75 Ge 0.25 and cSi 0.65 Ge 0.35 p-and n-channel compressively strained Silicon-Germanium on Insulator (cSGOI) MOSFETs with 15nm thick SiGe films and with TiN/HfO 2 /SiO 2 gate stacks, obtained using the enrichment technique. In strong inversion, front and back interface current noise in PMOSFET devices is described using the N model, whereas NMOSFET noise is described using the N-µ model . In weak inversion, the noise behavior deviates from these standard models. We observe an impact of the back interface noise source on the front interface one and vice versa. Thus, the interface trap densities and the Coulomb scattering parameters are extracted. The obtained interface trap densities values demonstrate the good quality of both interfaces.

Solid-State Electronics, 2013

In this paper, we present the modeling of low frequency noise of FD SOI devices in the front and ... more In this paper, we present the modeling of low frequency noise of FD SOI devices in the front and back interface channel operations. We present an analytical model for the inversion charge power spectral density in FD SOI MOSFETs. This analytical model is valid for the different modes of operation of the device, in both the front and back conduction regimes. The simulation results are compared to those obtained using our numerical model presented in a previous work and to experimental data. A very good agreement between both models and the measurements is obtained. We show that when only the back channel is activated, the influence of the front oxide noise contribution can be neglected

Solid-State Electronics, 2002

Low frequency noise has been studied from the weak to strong inversion regime in n-channel MOS tr... more Low frequency noise has been studied from the weak to strong inversion regime in n-channel MOS transistors. The 1=f current noise power spectrum density S ID is measured as a function of the drain current and gate voltage with the gate length as a parameter. Analysis of the noise characteristics shows that the channel noise agrees with the mobility fluctuation model and can be predicted in the linear and saturation region using the a H parameter only. Finally, the three parameters NOIA, NOIB and NOIC used in the BSIM3v3 noise model are extracted. Some discrepancies of the noise simulation with the experimental data are observed. Ó

Microelectronics Reliability, 2000

ABSTRACT Low-frequency noise measurements are performed in two types of low temperature polysilic... more ABSTRACT Low-frequency noise measurements are performed in two types of low temperature polysilicon thin film transistors (TFTs). For the first TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility fluctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the fluctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite different from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering.

Microelectronic Engineering, 2011

In this paper, we present a new numerical model of the inversion charge power spectral density in... more In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.

Microelectronic Engineering, 2011

This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Ge... more This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Germanium-On-Insulator (GeOI) PMOS transistors processed on different wafers. The wafers are obtained by Ge enrichment technique and by Smart Cut™ technology. The slow oxide trap densities of back interface are used as a figure of merit to evaluate the process. The Smart Cut™ process is evaluated by studying

Microelectronic Engineering, 2007

Journal of Applied Physics, 1998

ABSTRACT Conduction and low-frequency noise are analyzed in hydrogenated amorphous thin film tran... more ABSTRACT Conduction and low-frequency noise are analyzed in hydrogenated amorphous thin film transistors with small channel length. From current–voltage characteristics a set of conduction parameters is extracted pointing out parasitic resistances in series with the active channel. The low-frequency noise behavior is studied by means of the small equivalent circuit of the device. Intrinsic channel noise is separated from access resistance noise. Channel noise variations versus device biases agree with Hooge’s theory (carrier mobility fluctuations) but the noise levels are greater than in crystalline metal-oxide-semiconductor transistors. For high drain current 1/f noise in access series resistances prevails and becomes the main noise source. So, the results show the important part taken by these resistances in conduction and noise. Some comments for the design of thin film transistors are given. © 1998 American Institute of Physics.

Journal of Applied Physics, 2002

Conduction and low frequency channel noise of gallium-arsenide (GaAs) based pseudomorphic high el... more Conduction and low frequency channel noise of gallium-arsenide (GaAs) based pseudomorphic high electron mobility transistors are investigated. The following analysis takes into account both the noise source associated with the intrinsic part of the device and the sources located within the access path. In order to discriminate between these two noise origins, a model of the transistor conduction is proposed using only a few parameters which are easily extracted. It is shown that the intrinsic channel noise agrees with Hooge's model with alphaH parameter about 3×10-4 for the studied technology. Moreover, the values of the access resistances are an important parameter to describe correctly the conduction and the noise behaviors.

IEE Proceedings - Circuits, Devices and Systems, 2004

An overview of theoretical 1/f noise models is given. Analytical expressions showing the device g... more An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the DN model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.

IEEE Electron Device Letters, 2000

For the first time the effect of increasing the Schottky barrier's Al content of InP-based InAlAs... more For the first time the effect of increasing the Schottky barrier's Al content of InP-based InAlAs-InGaAs HEMT's from 48 to 60% on the low-frequency (LF) drain and gate current noise is investigated. It is shown that the LF gate current noise S S

30th European Solid-State Device Research Conference, 2000

ABSTRACT First Page of the Article

Channel noise of MOS integrated tetrodes is investigated versus frequency and bias. The behavior ... more Channel noise of MOS integrated tetrodes is investigated versus frequency and bias. The behavior is analyzed in the four operation modes taking into account the variations of the small signal parameters. Voltage-gain and noise figure are simultaneously measured. The two inputs are investigated. Experimental results and their interpretations lead to the bias range giving the best compromise between high voltage-gain and low noise figure.

2011 - 14th International Symposium on Electrets, 2011

ABSTRACT In this work, the authors demonstrate that the meta-stable DRAM (MSDRAM) can achieve bet... more ABSTRACT In this work, the authors demonstrate that the meta-stable DRAM (MSDRAM) can achieve better performances regarding to the sensing margin compared to programming methods like impact ionization and forward biased junctions. This improvement results mainly from the low current level at 0-state. Indeed, the MSDRAM uses gate capacitive coupling method which allows to reach zero current level. Finally, the band-to-band tunneling used to program the 1-state strongly reduces the power consumption and improves the device reliability. These promising results promote the meta-stable dip (MSD) programming mechanism as a viable solution for low power single-transistor DRAM memories.

2011 21st International Conference on Noise and Fluctuations, 2011

This paper presents low-frequency noise in Si 0.75 Ge 0.25 and Si 0.65 Ge 0.35 p-and n-channel st... more This paper presents low-frequency noise in Si 0.75 Ge 0.25 and Si 0.65 Ge 0.35 p-and n-channel strained Germanium on Insulator (SGOI) MOSFETs with 15nm thick substrates and with TiN/HfO 2 /SiO 2 gate stacks, obtained using the enrichment technique. In strong inversion, front and back interface current noise in PMOSFET devices is described using the ∆ ∆ ∆ ∆N model, whereas NMOSFET noise is described using the ∆ ∆ ∆ ∆N-∆ ∆ ∆ ∆µ model, with a ten-fold increase in noise in some cases. In weak inversion, the noise behavior deviates from these standard models and may be described by noise coupling between the two interfaces. For both types of device, the extracted densities are approximately the same, with no significant impact from the variation of the Ge content.

Noise in Devices and Circuits, 2003

Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE,... more Three standard 1/f noise models for MOSFETs are actually implemented in software packages: SPICE, HSPICE and recently BSIM3v3 noise model. The aim of this contribution is to show the limitation for each of these implementations by comparing noise simulations to noise measurement data.

Noise in Physical Systems and 1/f Fluctuations - ICNF 2001 - Proceedings of the 16th International Conference, 2001

Microelectronics Reliability, 2007

ABSTRACT This paper presents the electrical characterization of thick and thin SiO2 oxynitride pe... more ABSTRACT This paper presents the electrical characterization of thick and thin SiO2 oxynitride performed by thermal and plasma nitridation processes. The impact of the nitridation technique is investigated using random telegraph signal (RTS) noise analysis. The variation of the gate oxide trap characteristics is determined with respect to the nitridation technique. Significant properties of traps are also pointed out. Main trap parameters, such as their depth with respect to the interface, nature, capture and emission times are extracted. These results illustrate the potential of RTS noise investigation for gate oxide characterizations.

Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is ... more Using a compact model derived for long channels ΠFET, TGFETs and planar FDSOI transistors, it is demonstrated that experimental fully depleted devices can operate in the 'back-interface inversion' regime even at VG2 grounded. As a result, two threshold voltages appear in the transistors, with an experimental difference of threshold voltages up to several hundreds mV for planar FDSOI devices. As

Gate and drain current /f noise parameters have been extracted in p-metal-oxide-semiconductor tra... more Gate and drain current /f noise parameters have been extracted in p-metal-oxide-semiconductor transistors processed with two nitridation techniques (RTN or DPN). The drain noise magnitude allows extraction of the slow oxide trap density Nt(EF) in the range of 3 1017 eV-1 cm-3. We don't observe any improvement of the /f noise performance for DPN devices, which is in opposition with the trends observed on thicker oxides. 1/f gate current noise has been also investigated for these devices, and similar results have been obtained concerning the /f noise levels. The benefit in changing process for thick oxide doesn't hold any longer in term on /f noise performance with an equivalent oxide thickness of 1.2 nm.

Solid-State Electronics, 2012

This paper presents low-frequency noise in cSi 0.75 Ge 0.25 and cSi 0.65 Ge 0.35 p-and n-channel ... more This paper presents low-frequency noise in cSi 0.75 Ge 0.25 and cSi 0.65 Ge 0.35 p-and n-channel compressively strained Silicon-Germanium on Insulator (cSGOI) MOSFETs with 15nm thick SiGe films and with TiN/HfO 2 /SiO 2 gate stacks, obtained using the enrichment technique. In strong inversion, front and back interface current noise in PMOSFET devices is described using the N model, whereas NMOSFET noise is described using the N-µ model . In weak inversion, the noise behavior deviates from these standard models. We observe an impact of the back interface noise source on the front interface one and vice versa. Thus, the interface trap densities and the Coulomb scattering parameters are extracted. The obtained interface trap densities values demonstrate the good quality of both interfaces.

Solid-State Electronics, 2013

In this paper, we present the modeling of low frequency noise of FD SOI devices in the front and ... more In this paper, we present the modeling of low frequency noise of FD SOI devices in the front and back interface channel operations. We present an analytical model for the inversion charge power spectral density in FD SOI MOSFETs. This analytical model is valid for the different modes of operation of the device, in both the front and back conduction regimes. The simulation results are compared to those obtained using our numerical model presented in a previous work and to experimental data. A very good agreement between both models and the measurements is obtained. We show that when only the back channel is activated, the influence of the front oxide noise contribution can be neglected

Solid-State Electronics, 2002

Low frequency noise has been studied from the weak to strong inversion regime in n-channel MOS tr... more Low frequency noise has been studied from the weak to strong inversion regime in n-channel MOS transistors. The 1=f current noise power spectrum density S ID is measured as a function of the drain current and gate voltage with the gate length as a parameter. Analysis of the noise characteristics shows that the channel noise agrees with the mobility fluctuation model and can be predicted in the linear and saturation region using the a H parameter only. Finally, the three parameters NOIA, NOIB and NOIC used in the BSIM3v3 noise model are extracted. Some discrepancies of the noise simulation with the experimental data are observed. Ó

Microelectronics Reliability, 2000

ABSTRACT Low-frequency noise measurements are performed in two types of low temperature polysilic... more ABSTRACT Low-frequency noise measurements are performed in two types of low temperature polysilicon thin film transistors (TFTs). For the first TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility fluctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the fluctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite different from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering.

Microelectronic Engineering, 2011

In this paper, we present a new numerical model of the inversion charge power spectral density in... more In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.

Microelectronic Engineering, 2011

This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Ge... more This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Germanium-On-Insulator (GeOI) PMOS transistors processed on different wafers. The wafers are obtained by Ge enrichment technique and by Smart Cut™ technology. The slow oxide trap densities of back interface are used as a figure of merit to evaluate the process. The Smart Cut™ process is evaluated by studying

Microelectronic Engineering, 2007

Journal of Applied Physics, 1998

ABSTRACT Conduction and low-frequency noise are analyzed in hydrogenated amorphous thin film tran... more ABSTRACT Conduction and low-frequency noise are analyzed in hydrogenated amorphous thin film transistors with small channel length. From current–voltage characteristics a set of conduction parameters is extracted pointing out parasitic resistances in series with the active channel. The low-frequency noise behavior is studied by means of the small equivalent circuit of the device. Intrinsic channel noise is separated from access resistance noise. Channel noise variations versus device biases agree with Hooge’s theory (carrier mobility fluctuations) but the noise levels are greater than in crystalline metal-oxide-semiconductor transistors. For high drain current 1/f noise in access series resistances prevails and becomes the main noise source. So, the results show the important part taken by these resistances in conduction and noise. Some comments for the design of thin film transistors are given. © 1998 American Institute of Physics.

Journal of Applied Physics, 2002

Conduction and low frequency channel noise of gallium-arsenide (GaAs) based pseudomorphic high el... more Conduction and low frequency channel noise of gallium-arsenide (GaAs) based pseudomorphic high electron mobility transistors are investigated. The following analysis takes into account both the noise source associated with the intrinsic part of the device and the sources located within the access path. In order to discriminate between these two noise origins, a model of the transistor conduction is proposed using only a few parameters which are easily extracted. It is shown that the intrinsic channel noise agrees with Hooge's model with alphaH parameter about 3×10-4 for the studied technology. Moreover, the values of the access resistances are an important parameter to describe correctly the conduction and the noise behaviors.

IEE Proceedings - Circuits, Devices and Systems, 2004

An overview of theoretical 1/f noise models is given. Analytical expressions showing the device g... more An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the DN model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.

IEEE Electron Device Letters, 2000

For the first time the effect of increasing the Schottky barrier's Al content of InP-based InAlAs... more For the first time the effect of increasing the Schottky barrier's Al content of InP-based InAlAs-InGaAs HEMT's from 48 to 60% on the low-frequency (LF) drain and gate current noise is investigated. It is shown that the LF gate current noise S S