Joan Cabestany | Universitat Politecnica de Catalunya (original) (raw)

Papers by Joan Cabestany

Medical & Biological Engineering & Computing, 2015

Most partitioning algorithms have been developed for conventional programmable logic (especially ... more Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional density of circuits, but traditional partitioning techniques are not able to exploit the novel features offered by these devices. A new family of partitioning techniques for DRPL should be developed, being its main goal the maximisation of the functional density on balanced partition sizes. This paper presents a new partitioning algorithm based on a temporal separation of the system functionality. As our experimental results will show, the algorithm is able to benefit from the dynamic reconfiguration properties of FPGA devices.

In this paper we address the problem of constructing efficient hardware solutions for Region of i... more In this paper we address the problem of constructing efficient hardware solutions for Region of influence (ROI) incremental algorithms. First we shall review the main features associated with these neural models, paying special attention to the basic operations required in order to fulfil the data flow imposed by their training and recall phases. Taking into account the resource organization demanded by this data flow, we shall propose an efficient digital realization which is capable to convert into a physical implementation the organization principles stated previously. The proposed realization is composed of a bidimensional array of processing units, which have been developed as RISC processors. After explaining the emulation sequence to be used for ROI incremental models on the proposed realization, we evaluate the performance (measured in terms of processing speed) attainable by the system when real world classification tasks have to be handled. Our results shown that the proposed realization considerably outperforms recent commercial developments.

IEEE Transactions on Biomedical Engineering, 2007

Journal of Neural Engineering, 2005

Multielectrode array technology constitutes a promising approach for the characterization of the ... more Multielectrode array technology constitutes a promising approach for the characterization of the activity-dependent neuronal plasticity underlying information processing in the nervous system. For this purpose, long-term monitoring and stimulation of cultured neuronal networks with one-to-one neuron-sensor interfacing is advantageous. Existing neurochips that meet these specifications have made use of custom 3D structures requiring clean-room intensive microfabrication techniques. Low-cost fabrication procedures with potential for mass production would facilitate progress in the area. To this end, we have developed a sandwich structure comprising an elastomeric film, microstructured by replica moulding and microhole punching, for neuronal patterning, and a standard planar microelectrode array (MEA), for stimulation and recording. The elastomeric film includes microwells for cell body confinement, and microchannels capable of guiding neurites for network topology specification. The device is formed by overlaying the elastomeric structures on planar arrays. The combination of replica moulding, rapid prototyping and planar MEAs results in low-cost neurochips accessible to most neurophysiology labs. Single neuron patterning and recordings of extracellular potentials are demonstrated.

A novel approach to design low cost/high performance on-line physiological data and water monitor... more A novel approach to design low cost/high performance on-line physiological data and water monitoring systems is presented and discussed. The approach is based on a set of solid state chemical sensors (i.e. ISFETs/CHEMFETs), and a post-processing stage which performs the estimation of the ionic activities presented in the solution. This estimation is performed by a non-linear blind separation algorithm that uses some prior knowledge about how sensors simultaneously respond to several ionic activities. Additionally, the presented approach addresses some important problems of these sensors like temperature effects, cross sensitivity and drift; it also takes into account some hardware implementation constraints. Experimental results confirm the effectiveness of the proposed architecture.

Sensors and Actuators B-chemical, 2006

Neural Processing Letters, 2001

Neural Networks, 2001

Large margin classifiers (such as MLPs) are designed to assign training samples with high confide... more Large margin classifiers (such as MLPs) are designed to assign training samples with high confidence (or margin) to one of the classes. Recent theoretical results of these systems show why the use of regularisation terms and feature extractor techniques can enhance their generalisation properties. Since the optimal subset of features selected depends on the classification problem, but also on the particular classifier with which they are used, global learning algorithms for large margin classifiers that use feature extractor techniques are desired. A direct approach is to optimise a cost function based on the margin error, which also incorporates regularisation terms for controlling capacity. These terms must penalise a classifier with the largest margin for the problem at hand. Our work shows that the inclusion of a PCA term can be employed for this purpose. Since PCA only achieves an optimal discriminatory projection for some particular distribution of data, the margin of the classifier can then be effectively controlled. We also propose a simple constrained search for the global algorithm in which the feature extractor and the classifier are trained separately. This allows a degree of flexibility for including heuristics that can enhance the search and the performance of the computed solution. Experimental results demonstrate the potential of the proposed method.

Neural Processing Letters, 2004

Electrochemical sensors, like ion-selective field transistors (ISFET), are electronic devices tha... more Electrochemical sensors, like ion-selective field transistors (ISFET), are electronic devices that merge solid-state electronic technology with chemical sensors so as to be sensitive to the concentration of a particular ion in a solution. However, as it has been previously reported, their response does not only depend on a single ion but also is affected by several interfering ions found in the solution to be measured. These interfering ions can be considered as noise and consequently, a post-processing stage that increases the SNR is obligatory. Our work shows how ensemble learning methods could be used in an array of chemical sensors in order to deal with this problem. In particular, we introduce a novel neural learning architecture for ISFET arrays, which employ ISFET models as prior knowledge. The proposed ensemble learning systems are RBF-like solutions based on bagging and optimal linear combination. Several experimental results are included, which demonstrate the interest and viability of the proposed solution.

Pattern Recognition, 2000

FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid proto... more FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid prototyping of electronic systems. After a description of its architecture and associated development tools, its distinguishing features are highlighted. In particular, integration of a microprocessor, programmable logic and configurable analog channels in the same chip provides a monolithic platform with capability to prototype complete

A structure to improve the e-beam logic testability of complex VLSI and wafer-scale integration (... more A structure to improve the e-beam logic testability of complex VLSI and wafer-scale integration (WSI) circuits is proposed. This structure makes possible the generation of internal logic states without any extra external connection pads by means of a low-energy and observation-compatible electron beam. Since these internal logic states reflect the presence/absence of the electron beam on a point of the

In this paper we address the problems posed when Artificial Neural Networks models are implemente... more In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The dynamic reconfiguration properties (i.e., the possibility to change the functionality of the system in real time) of a new family of programmable devices called FIPSOC (Field Programmable System On a Chip) offer an efficient alternative (both in terms of area and speed) for implementing hardware accelerators. After presenting the data flow associated with a serial arithmetic unit, we shall show how its dynamic implementation in the FIPSOC device is able to outperform systems realised in conventional programmable devices.

The design of a digital neural processor based on a VLSI architecture is discussed. Each processo... more The design of a digital neural processor based on a VLSI architecture is discussed. Each processor is an element of a systolic array capable of performing the backpropagation algorithm. The processor's internal structure and its characteristics are discussed