Simulation and Synthesis Model for the Addition of Single Precision Floating Point Numbers Using VERILOG (original) (raw)
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International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/simulation-and-synthesis-model-for-the-addition-of-single-precision-floating-point-numbers-using-verilog https://www.ijert.org/research/simulation-and-synthesis-model-for-the-addition-of-single-precision-floating-point-numbers-using-verilog-IJERTV2IS90913.pdf 1. Abstract Single Precision floating point adder designed to fully conform to the IEEE 754 standard. In its fully-featured format, this adder supports all rounding modes: round to nearest even, round to plus infinity, round to minus infinity, and round to zero; it supports de-normalized numbers as both input and output; it supports all applicable exception flags: overflow, underflow, inexact, and invalid; it supports trapped overflow and underflow, where the result is returned with an additional bias applied to the exponent. The main objectives of the paper are the following is to design an adder for two positive floating point binary numbers which support all rounding modes.Therefore, Verilog programming for IEEE single precision floating point multiplier module have been explored.
IJERT-Design and Simulation of Double Precision Floating-Point Adder
International Journal of Engineering Research and Technology (IJERT), 2015
https://www.ijert.org/design-and-simulation-of-double-precision-floating-point-adder https://www.ijert.org/research/design-and-simulation-of-double-precision-floating-point-adder-IJERTV4IS100560.pdf Floating point numbers are very important part of computer processing. Addition imposes a great challenge due to its processing time. This paper presents a technique for addition of IEEE 754 double precision floating-point numbers within two clock cycles. This paper results also show improvements in power utilization, operational chip area management and optimization of hardware. This proposed adder is implemented with the help of 6slx45tfgg484-3 Spartan family as well as 5vfx70tff1136-1 of Virtex Xilinx FPGA devices.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Precision Format
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high-end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating point adder with minimum time. Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL. This paper discusses in detail the best possible FPGA implementation will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/design-and-simulation-of-pipelined-double-precision-floating-point-addersubtractor-and-multiplier-using-verilog https://www.ijert.org/research/design-and-simulation-of-pipelined-double-precision-floating-point-addersubtractor-and-multiplier-using-verilog-IJERTV3IS10099.pdf A floating-point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. This paper presents FPGA implementation of a single unit named Adder/Subtractor which is able to perform both double precision floating point addition and subtraction and a double precision floating point multiplier. Both the design is based on pipelining so the overall throughput is increased. Both units are implemented using Verilog and the code is dumped into vertex-5 FPGA.
IJERT-Design of IEEE-754 Double Precision Floating Point Unit Using Verilog
International Journal of Engineering Research and Technology (IJERT), 2014
https://www.ijert.org/design-of-ieee-754-double-precision-floating-point-unit-using-verilog https://www.ijert.org/research/design-of-ieee-754-double-precision-floating-point-unit-using-verilog-IJERTV3IS041272.pdf Floating point addition, subtraction and multiplication are widely used in large set of scientific and signal processing computation. Thus an IEEE-754 double precision floating point unit (FPU) is designed in this paper. The proposed design involves logarithmic approach for computing floating point numerical operations. It performs all the four basic arithmetic operations that also handle overflow, underflow, rounding and various exception conditions. The design is coded in Verilog hardware description language and simulated in Questasim.
IJERT-An fpga based double precision floating point arithmetic unit using verilog
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/an-fpga-based-double-precision-floating-point-arithmetic-unit-using-verilog https://www.ijert.org/research/an-fpga-based-double-precision-floating-point-arithmetic-unit-using-verilog-IJERTV2IS100200.pdf Floating point unit (FPU) addition, subtraction, multiplication and division are widely used in large set of scientific, commerce, financial and in signal processing computation. A high speed floating point double precision adder/subtractor, multiplier and divider are implemented on a Virtex-7 Fpga. In addition /subtractor unit, the proposed designs are compliant with IEEE-754 format and handles overflow, underflow, rounding and various exception conditions. The proposed FPU designs have achieved the operating frequencies of 371.858 MHz while sequential execution of all the operations with a selected inputs given through a test bench.All the modules are realized and validated using Verilog simulation in the Model sim and synthesized using Xilinx 14.1 ISE software
IJERT-Design of High Performance IEEE- 754 Single Precision (32 bit) Floating Point Adder Using VHDL
International Journal of Engineering Research and Technology (IJERT), 2013
https://www.ijert.org/design-of-high-performance-ieee-754-single-precision-32-bit-floating-point-adder-using-vhdl https://www.ijert.org/research/design-of-high-performance-ieee-754-single-precision-32-bit-floating-point-adder-using-vhdl-IJERTV2IS70837.pdf Floating Point arithmetic is by far the most used way of approximating real number arithmetic for performing numerical calculations on modern computers. The advantage of floating-point representation over fixed-point and integer representation is that it can support a much wider range of values. Addition/subtaraction,Multiplication and division are the common arithmetic operations in these computations.Among them Floating point Addition/Subtraction is the most complex one.This paper implements an efficient 32bit floating point adder according to ieee 754 standard with optimal chip area and high performance using VHDL .The proposed architecture is implemented on Xilinx ISE Simulator.Results of proposed architecture are compared with the existed architecture and have observed reduction in area and delay. Further, this project can be extendable by using any other type of faster adder in terms of area, speed and power.
FPGA based implementation of a double precision IEEE floating-point adder
2013 7th International Conference on Intelligent Systems and Control (ISCO), 2013
Floating-Point addition imposes a great challenge during implementation of complex algorithm in hard real time due to the enormous computational burden associated with repeated calculations with high precision numbers. Moreover, at the hardware level, any basic addition or subtraction circuit has to incorporate the alignment of the significands. This paper presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. The proposed technique has exhibited improvement in the latency and also in the operational chip area management. The proposed double precision IEEE floating-point adder has been implemented with XC2V6000 and XC3SI500 Xilinx © FPGA devices.
Design and Implementation of Floating-Point Addition and Floating-Point Multiplication
International Journal for Research in Applied Science & Engineering Technology (IJRASET), 2022
In this paper, we present the design and implementation of Floating point addition and Floating point Multiplication. There are many multipliers in existence in which Floating point Multiplication and Floating point addition offers a high precision and more accuracy for the data representation of the image. This project is designed and simulated on Xilinx ISE 14.7 version software using verilog. Simulation results show area reduction and delay reduction as compared to the conventional method.
2012
This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor using IEEE 754-2008 format. In this paper we describe an efficient implementation of an IEEE 754 single precision Standard for Binary Floating- Point Arithmetic to include specifications for decimal floating-point arithmetic. As processor support for decimal floating-point arithmetic emerges, it is important to investigate efficient algorithms and hardware designs for common decimal floating- point arithmetic algorithms. This paper presents novel designs for a decimal floating-point addition and subtraction. They are fully synthesizable hardware descriptions in VERILOG. Each one is presented for high speed computing.