A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance (original) (raw)
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IEEE Transactions on Circuits and Systems I: Regular Papers, 2008
This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
IEEE Journal of Solid-State Circuits, 2002
This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the linearized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25m CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10 13 when the magnitude of data jitter reaches 60.5% of a bit time.
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
IEEE Journal of Solid-State Circuits, 2018
We present a technique to measure random jitter in a phase interpolator (PI)-based clock and data recovery (CDR) circuit by injecting a controlled amount of square-wave jitter into its edge clock and monitoring its effect on the autocorrelation function of the CDR's bang-bang phase detector output. Jitter is injected by adjusting the code of the edge PI while the autocorrelation function is measured by on-chip counters. Since the injected jitter only affects the edge clock, the CDR remains operational during jitter injection. Using this technique, the rms relative jitter between the clock and data at the CDR input can be estimated with sub-picosecond accuracy as demonstrated in measurements of a 28 Gb/s half-rate digital CDR fabricated in 28 nm CMOS.
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs
IEEE Journal of Solid-State Circuits, 2015
On-chip jitter measurement can be used to optimize the performance of wireline transceivers. In this work, the jitter of random data is measured on-chip by correlating the phase detector outputs from two adjacent CDR lanes. This allows the jitter's autocorrelation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. The RMS value of random jitter ranging from 0.85 ps to 1.89 ps, and sinusoidal jitter from 0.89 ps to 5.1 ps is measured in PRBS31 data with less than 0.6 ps of error compared to measurements by an 80 GS/s real-time oscilloscope. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the recovered clock jitter. Sinusoidal jitter from 1.8 ps to 5.3 ps is measured in the recovered clock with an error of less than 1 ps. Index Terms-Clock and data recovery, CDR, jitter, jitter measurement, on-chip measurement.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-. With input 10-Gb/s data of a PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage. Index Terms-Bang-bang phase detector (BBPD), clock and data recovery (CDR), frequency detector (FD).
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit
IEEE Journal of Solid-state Circuits, 2006
A 200-Mbps 2-Gbps continuous-rate clock-anddata-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2 31 1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10 12 . The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.
A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit
IEEE Transactions on Circuits and Systems I-regular Papers, 2006
A 200-Mbps 2-Gbps continuous-rate clock-anddata-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2 31 1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10 12 . The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.
Unifying approach for jitter transfer analysis of bang-bang CDR circuits
Electronics and Information …, 2010
AbstractClock and data recovery (CDR) circuits using bang-bang phase detectors (BBPDs) are widely used in high speed serial links. The BBPD quantizes the phase difference between the input data and the recovered clock, generating a two state output for the loop ...
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit
IEEE Transactions on Circuits and Systems I-regular Papers, 2006
A 200-Mbps 2-Gbps continuous-rate clock-anddata-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2 31 1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10 12 . The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.
IEEE Journal of Solid-State Circuits, 2006
A 0.25-m CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge detector with a continuous-time first-order Sigma-Delta analog-to-digital converter, and a hybrid loop filter that contains an analog feedforward path and digital integrating path. In addition, an all-digital frequency acquisition method that does not require a reference frequency, quadrature phases from the VCO, or a significant amount of high-speed logic is presented. A nice byproduct of the frequency acquisition circuitry is that it also provides an estimate of the bit error rate (BER) experienced by the CDR. The CDR exceeds all SONET performance requirements at 155-, 622-, and 2500-Mb/s as well as Gigabit Ethernet specifications at 1.25 Gb/s. The chip operates with either a 2.5-or 3.3-V supply, consumes a maximum of 197 mA across all data rates, and fits in a 5 5 mm package.