On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs (original) (raw)
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On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
IEEE Journal of Solid-State Circuits, 2018
We present a technique to measure random jitter in a phase interpolator (PI)-based clock and data recovery (CDR) circuit by injecting a controlled amount of square-wave jitter into its edge clock and monitoring its effect on the autocorrelation function of the CDR's bang-bang phase detector output. Jitter is injected by adjusting the code of the edge PI while the autocorrelation function is measured by on-chip counters. Since the injected jitter only affects the edge clock, the CDR remains operational during jitter injection. Using this technique, the rms relative jitter between the clock and data at the CDR input can be estimated with sub-picosecond accuracy as demonstrated in measurements of a 28 Gb/s half-rate digital CDR fabricated in 28 nm CMOS.
Jitter injection for on-chip jitter measurement in PI-based CDRs
2017 IEEE Custom Integrated Circuits Conference (CICC), 2017
We propose a technique to estimate the relative jitter between the input data and recovered clock of a 28Gb/s half-rate digital PI-based CDR without using an eye monitor. Instead, we inject square wave jitter with a known amplitude into the CDR, by adding a corresponding signal to the CDR's PI code. By measuring the effect of the injected jitter on the autocorrelation function of the CDR's bang-bang PD output, the RMS relative jitter is estimated with sub-picosecond accuracy, as demonstrated with a test chip fabricated in 28nm CMOS.
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance
IEEE Journal of Solid-State Circuits, 2007
This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.
Receiver jitter tracking characteristics in high-speed source synchronous links
2011
High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10 Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator-(PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2008
This paper describes the modeling of jitter in clock-and-data recovery (CDR) systems using an event-driven model that accurately includes the effects of power-supply noise, the finite bandwidth (aperture window) in the phase detector's front-end sampler, and intersymbol interference in the system's channel. These continuous-time jitter sources are captured in the model through their discrete-time influence on sample based phase detectors. Modeling parameters for these disturbances are directly extracted from the circuit implementation. The event-driven model, implemented in Simulink, has a simulation accuracy within 12% of an Hspice simulation-but with a simulation speed that is 1800 times higher.
Clock jitter estimation based on PM noise measurements
IEEE International Frequency Control Sympposium and PDA Exhibition Jointly with the 17th European Frequency and Time Forum, 2003. Proceedings of the 2003
-"Jitter" is the noise modulation due to random time shifts on an otherwise ideal, or perfectly on-time, signal transition. In the absence of ultra-high-speed jitter analyzers, spectrum analysis is an alternate noise measurement for timing jitter. Conventionally, jitter has been defined as a the integral of the phase noise. This paper presents a modified way of calculating timing jitter using phasemodulation (PM) noise measurements of high-speed digital clocks, which considers the frequency response of the jitter analyzer, providing a more accurate map. Measurements of phase noise are typically much more sensitive to phase (or time) fluctuations than a jitter analyzer. A summary table is provided for mapping the results of these measurements in the Fourier frequency domain to jitter in the τ domain for various random (specifically, power-law) noise types, spurs, vibration, and power-supply ripple. In general, one cannot unambiguously map back, that is, translate from jitter measurements to phase noise.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-. With input 10-Gb/s data of a PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage. Index Terms-Bang-bang phase detector (BBPD), clock and data recovery (CDR), frequency detector (FD).
A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects
IEEE Journal of Solid-State Circuits, 2000
This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of 10 12 and tracks frequency deviations between the incoming data and the reference clock of up to 122 ppm. The sinusoidal jitter tolerance is 0.35 UI pp for jitter frequencies 100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UI pp at a BER = 10 12 . The core CDR circuit occupies a chip area of 0.07 mm 2 and consumes 98 mW from a 1.1-V supply.
Unifying approach for jitter transfer analysis of bang-bang CDR circuits
Electronics and Information …, 2010
AbstractClock and data recovery (CDR) circuits using bang-bang phase detectors (BBPDs) are widely used in high speed serial links. The BBPD quantizes the phase difference between the input data and the recovered clock, generating a two state output for the loop ...
Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems
2007 IEEE Electrical Performance of Electronic Packaging, 2007
Although it is well understood that a band-limited passive system can be a source of deterministic jitter, it is less obvious that the deterministic and random jitters generated by the clock or data source can be enhanced significantly by the passive channel. In this paper, modeling and simulation techniques to predict jitter enhancement across interconnect systems are presented. The conventional method of using SPICE to calculate output jitter is computationally expensive. Instead, the effect of channel on input jitter can be represented by jitter impulse response or jitter transfer function in time or frequency domains, respectively. These jitter characteristic functions can then be used to efficiently determine the increase in jitter as signal propagates across an interconnect system. The probability mass function of jitter impulse response can also be constructed to statistically predict the jitter enhancement at lower bit-error rate. Finally, the results form SPICE-based simulation and those obtained using the jitter characteristic functions are compared.