A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective (original) (raw)
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Rapid design space exploration for multi parametric optimization of VLSI designs
IEEE International Symposium on Circuits and Systems, 2010
Design Space Exploration (DSE) is one of the most important stages in High Level Synthesis designing methodology. This paper presents a novel DSE approach for the current generation of systems with heterogeneous multi parametric optimization objectives. The method introduced in this paper is capable of concurrently resolving multiple conflicting issues encountered during DSE, such as maximization of accuracy needed in the evaluation of design space with minimization in time expended to explore the best architecture. Results of the proposed method for different benchmarks indicated significant acceleration in exploration process compared to another existing approach that is also based on Pareto optimal analysis. 978-1-4244-5309-2/10/$26.00 ©2010 IEEE
Expert Systems with Applications, 2014
A novel algorithm for automated simultaneous exploration of datapath and Unrolling Factor (UF) during power-performance tradeoff in High Level Synthesis (HLS) using multi-dimensional particle swarm optimization (PSO) (termed as 'M-PSO') for control and data flow graphs (CDFGs) is presented. The major contributions of the proposed algorithm are as follows: (a) simultaneous exploration of datapath and loop UF through an integrated multi-dimensional particle encoding process using swarm intelligence; (b) an estimation model for computation of execution delay of a loop unrolled CDFG (based on a resource configuration visited) without requiring to tediously unroll the entire CDFG for the specified loop value in most cases; (c) balancing the tradeoff between power-performance metrics as well as control states and execution delay during loop unrolling; (d) sensitivity analysis of PSO parameter such as swarm size on the impact of exploration time and Quality of Results (QoR) of the proposed design space exploration (DSE) process. This analysis presented would assist the designer in pre-tuning the PSO parameters to an optimum value for achieving efficient exploration results within a quick runtime; (e) analysis of design metrics such as power, execution time and number of control steps of the global best particle found in every iteration with respect to increase/decrease in unrolling factor. The proposed approach when tested on a variety of data flow graphs (DFGs) and CDFGs indicated an average improvement in QoR of >28% and reduction in runtime of >94% compared to recent works.
Canadian Conference on Electrical and Computer Engineering, 2011
This paper presents a novel power efficient iterative Design Space Exploration (DSE) approach that finds the integrated solution to optimal/near-optimal scheduling and module selection with simultaneous reduction of the static power consumption of the design under the expenditure of minimal control steps. This iterative heuristic method is based on a novel priority function metric called 'Priority Indicator (PI)' and 'Dependency Matrix algorithm' that is responsible to minimize the power consumption of the resources without disturbing the data dependency present in the given problem. The proposed method also evenly distributes the allocated hardware functional units during the final scheduling. The comparison of the proposed approach with a recent approach in terms of exploration runtime and quality of final solution (measured using proposed 'Effective Cost Metric (ECM)') indicated an average improvement of 4.27 % in the quality of final solution and reduction of 62.52 % in exploration runtime.
A multi-objective genetic algorithm for design space exploration in high-level synthesis
2008
This paper presents a methodology for design space exploration (DSE) in high-level synthesis (HLS), based on a multi-objective genetic algorithm. Since all high-level synthesis sub-tasks are notoriously NP-complete and interdependent and the design objectives are in conflict for nature, most of the already proposed approaches are not efficient in the exploration of this design space and not effective in the identification of different trade-offs. For these reasons, evolutionary algorithms can be considered as good candidates to tackle such difficult explorations.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015
Recently, the requirement of shortened design cycles has led to rapid development of High Level Synthesis (HLS) tools that convert system level descriptions in a high level language into efficient hardware designs. Due to the high level of abstraction, HLS tools can easily provide multiple hardware designs from the same behavioral description. Therefore, they allow designers to explore various architectural options for different design objectives. However, such exploration has exponential complexity, making it practically impossible to explore the entire design space. The conventional approaches to reduce the design space exploration (DSE) complexity do not analyze the structure of the design space to limit the number of design points. To fill such a gap, we explore the structure of the design space by analyzing the dependencies between loops and arrays. We represent these dependencies as a graph that is used to reduce the dimensions of the design space. Moreover, we also examine the access pattern of the array and utilize it to find the efficient partition of arrays for each loop optimization parameter set. The experimental results show that our approach provides almost the same quality of result as the exhaustive DSE approach while significantly reducing the exploration time with an average of speed-up of 14x.
A flexible framework for fast multi-objective design space exploration of embedded systems
2003
The evaluation of the best system-level architecture in terms of energy and performance is of mainly importance for a broad range of embedded SOC platforms. In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized microprocessor-based systems. The architectural design space is multi-objective, so our aim is to find all the Pareto-optimal configurations representing the best power-performance design trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration (DSE) framework tuned to efficiently derive Pareto-optimal curves. The main characteristics of the proposed framework consist of its flexibility and modularity, mainly in terms of target architecture, related system-level executable models, exploration algorithms and system-level metrics. The analysis of the proposed framework has been carried out for a parameterized superscalar architecture executing a selected set of benchmarks. The reported results have shown a reduction of the simulation time of up to three orders of magnitude with respect to the full search strategy, while maintaining a good level of accuracy (under 4% on average).
Proceedings of the Great Lakes Symposium on VLSI 2022
Raising the level of VLSI design abstraction to the behavioral level allows to generate different micro-architectures from the same behavioral description by simply setting different synthesis options. These are typically synthesis directives in the form of pragmas that control how to synthesize arrays, loops, and functions. Out of all the combinations the designer is typically only interested in the synthesis directive combinations that lead to the Pareto-optimal designs. Unfortunately this multi-objective optimization problem grows supra-linearly with the number of the explorable operations. Thus, fast heuristics are needed. One additional way to accelerate the exploration process is by parallelizing the explorer tcreating multi-threaded versions. The main problem with this approach is that every time that a new pragma combination is generated the explorer requires to invoke the HLS process in order to evaluate the effect of these synthesis options on the resultant design. This tool invocation requires to check out a HLS tool license that will not be released until the HLS process has finished. This implies that the maximum number of parallel threads is limited by the number of licenses available. In the ASIC case, these licenses are extremely expensive, making it often prohibitory for some companies to have more than one. On contrary FPGA vendors provide their HLS tools free. Thus, it is tempting to investigate if FPGA HLS tools can be used to find the ASIC Pareto-optimal designs. To address this, in this work we present a dedicated multi-threaded parallel HLS DSE explorer that is able to accelerate HLS DSE for ASICs by targeting first FPGAs and using machine learning to convert the exploration results obtained to find the optimal ASIC equivalent. Experimental results show that our proposed approach is very efficient speedup up the exploration process considerably.
Transformation-based High Level Design Space Exploration1
1996
This paper describes a methodology for system level design. The starting point is a specification given as standard C program. After a HW/SW-codesign step, design space exploration is performed by examining several versions of the initial design created by means of high-level transformations. Our approach includes an acceleration of the design loop by replacing all tasks of physical design (especially the expensive task of logic synthesis) by a corresponding estimation step. For this, design space exploration can be carried out completely without considering physical design. A complete synthesis process has to be performed once for the only design identified for implementation within the design space exploration phase. The applicability of our methodology is demonstrated by means of an example application, the algorithm for computation of the discrete cosine transformation.
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures
IEEE International Symposium on Circuits and Systems, 2010
In High level Synthesis design methodology, the evaluation and selection of the optimal architecture for the system is done through a process called Design Space Exploration (DSE). This paper presents a novel framework for fast DSE using fuzzy search technique for optimizing modular computing architecture for the current generation of multi objective VLSI designs. The proposed method is able to radically reduce the number of architectural variants to be analyzed during design space exploration while simultaneously maintaining the precision required during the exploration process. Significant improvement in speedup during DSE is obtained for different benchmarks, compared to a DSE method with binary search mechanism.
Transformation-based High Level Design Space Exploration
This paper describes a methodology for system level design. The starting point is a specification given as standard C program. After a HW/SW-codesign step, design space exploration is performed by examining several versions of the initial design created by means of high-level transformations. Our approach includes an acceleration of the design loop by replacing all tasks of physical design (especially the expensive task of logic synthesis) by a corresponding estimation step. For this, design space exploration can be carried out completely without considering physical design. A complete synthesis process has to be performed once for the only design identified for implementation within the design space exploration phase. The applicability of our methodology is demonstrated by means of an example application, the algorithm for computation of the discrete cosine transformation.