Systematic Analysis of the High- and Low-Field Channel Mobility in Lateral 4H-SiC MOSFETs (original) (raw)

Scaling Between Channel Mobility and Interface State Density in SiC MOSFETs

… IEEE Transactions on, 2011

The direct impact of the SiO 2 /4H-SiC interface state density (D it ) on the channel mobility of lateral field-effect transistors is studied by tailoring the trap distribution via nitridation of the thermal gate oxide. We observe that mobility scales like the inverse of the charged state density, which is consistent with Coulomb-scattering-limited transport at the interface. We also conclude that the D it further impacts even the best devices by screening the gate potential, yielding small subthreshold swings and poor turn-ON characteristics.

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Microelectronic Engineering, 2006

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement. .es (A. Pérez-Tomás). www.elsevier.com/locate/mee Microelectronic Engineering 83 (2006) 440-445

Using a First Principles Coulomb Scattering Mobility Model for 4H-SiC MOSFET Device Simulation

Materials Science Forum, 2006

A physics based device simulator for detailed numerical analysis of 4H-SiC MOSFETs with an advanced mobility model that accounts for the effects of bulk and surface phonons, surface roughness and Coulomb scattering by occupied interface traps and fixed oxide charges, has been developed. A first principles quasi-2D Coulomb scattering mobility model specifically for SiC MOSFETs has been formulated. Using this, we have been able to extract the interface trap density of states profile for 4H-SiC MOSFETs and have shown that at room temperature, Coulomb scattering controls the total mobility close to the interface. High temperature, low field simulations and experiments show that the current increases with increase in temperature. The effect of Coulomb scattering decreases with increase in temperature causing an increase in the total mobility near the interface at low gate voltages.

Electron transport modeling in the inversion layers of 4H and 6H–SiC MOSFETs on implanted regions

Solid-State Electronics, 2005

In this work, we present the characterization of electron transport in 4H and 6H-SiC inversion layers with the development of a physics-based, 2-D quantum-mechanical model to explain the I DS -V GS , g m -V GS device electrical characteristics, the field-effect and conductivity mobility behaviors. The model considers the combined effects of surface roughness and Coulomb scattering centers arising from fixed oxide charge and interface trapped charge. The experimental characteristics in 6H and 4H-SiC MOSFETs, fabricated on implanted regions, are presented and interpreted with this model. The peak field-effect mobility values for the 4H and 6H-SiC MOSFETs are 45 and 50 cm 2 V À1 s À1 , respectively. The peak conductivity mobility for the 4H-SiC MOSFETs are 37 before and 220 cm 2 V À1 s À1 after correction for interface trapped charge. The I DS -V GS , g m -V GS , and the field-effect mobility are modeled to an accuracy of 3% in subthreshold and strong inversion regions.

Demonstration and analysis of channel mobility, trapped electron density and Hall effect at SiO2/SiC (0$\bar{3}$3$\bar{8}$) interfaces

Japanese Journal of Applied Physics, 2019

Low interface state density (D it) and high field-effect mobility (μ μ fe) at SiO 2 /4H-SiC (03̅ 38̅) Metal-oxide-semiconductor (MOS) interfaces are known. In order to understand the behavior and the scattering mechanisms induced electrons in more detail, we fabricated the Hall-bar lateral MOSFETs on the 4H-SiC (03̅ 38̅) substrate with various channel doping concentrations and evaluated the trapped electron densities and the Hall mobilities by split capacitance-voltage and Hall-effect measurements. Our results demonstrated that more than 80% of the induced electrons at the SiO 2 /4H-SiC MOS (03̅ 38̅) interfaces contribute to the current conduction as the free electrons. The majority of the electron traps seemed to be located mainly at the edge of the conduction band because the trapped electron density increased around the threshold voltage and was saturated in the high gate voltage region.

Advanced processing for mobility improvement in 4H-SiC MOSFETs: A review

Materials Science in Semiconductor Processing, 2018

This paper reviews advanced gate dielectric processes for SiC MOSFETs. The poor quality of the SiO 2 /SiC interface severely limits the value of the channel field-effect mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation methods are effective in increasing the channel mobility and have been adopted by manufacturers for the first generations of commercial power devices. Gate oxide doping techniques have also been successfully implemented to further increase the channel mobility, although device stability is compromised. The use of high-k dielectrics is also analyzed, together with the impact of different crystal orientations on the channel mobility. Finally, the performance of SiC MOSFETs in harsh environments is also reviewed with special emphasis on high temperature operation.

Channel mobility and on-resistance of vertical double implanted 4H-SiC MOSFETs at elevated temperatures

Semiconductor Science and Technology, 2009

Temperature and gate voltage dependences of the channel electron mobility were studied in short-channel high-voltage vertical double implanted 4H-SiC MOSFETs (VDMOSFETs). With increasing gate voltage, field effect electron mobility, μ FE , increased, tending to saturate at large V g values reaching a maximum of ∼4 cm 2 V −1 s −1 at room temperature. With the temperature increase, μ FE increased monotonically and reached a value of ∼16 cm 2 V −1 s −1 at 510 K. These trends are explained by the high density of the interface traps, which was extracted from the temperature dependence of the threshold voltage. The electron mobility in the drift region decreased with temperature increase. As a result, the contribution of the drift region to the on-resistance was dominant at elevated temperatures limiting the VDMOSFETs performance at temperatures above ∼420 K. The on-resistance of VDMOSFETs was only weakly dependent on temperature within the temperature range from 300 K to 510 K.

Interface state density and channel mobility for 4H-SiC MOSFETs with nitrogen passivation

Applied Surface Science, 2001

Interface state density and channel mobility have been characterized for 4H-SiC MOSFETs fabricated with dry thermal oxides and subsequently passivated with nitric oxide. The interface trap density at 0.1 eV below the conduction band edge decreases from approximately 8 Â 10 12 to 1 Â 10 12 eV À1 cm À2 following anneals in nitric oxide (NO) at 1175 8C for 2 h. The room temperature field effect channel mobility increases by an order of magnitude to approximately 35 cm 2 /V s following the passivation anneal. The field effect channel mobility of passivated MOSFETs shows almost no change with increasing temperature, while the mobility for unpassivated devices increases with increasing temperature and is thermally activated ($T 1.9 ) due to decreased Coulomb scattering by electrons trapped at the acceptor-like interface states near the conduction band. Over the temperature range 300-473 K, threshold voltage changes of about À0.8 and À3.7 V, respectively, are observed for devices processed with and without NO passivation. #