Extending UPPAAL for the Modeling and Verification of Dynamic Real-Time Systems (original) (raw)

Scenario-based verification of real-time systems using Uppaal

Formal Methods in System Design, 2010

This article proposes two approaches to tool-supported automatic verification of dense real-time systems against scenario-based requirements, where a system is modeled as a network of timed automata (TAs) or as a set of driving live sequence charts (LSCs), and a requirement is specified as a separate monitored LSC chart.

UPPAAL - a Tool Suite for Automatic Verification of Real-Time Systems

1995

Uppaal is a tool suite for automatic verification of safety and bounded liveness properties of real-time systems modeled as networks of timed automata. It includes: a graphical interface that supports graphical and textual representations of networks of timed automata, and automatic transformation from graphical representations to textual format, a compiler that transforms a certain class of linear hybrid systems to networks of timed automata, and a model-checker which is implemented based on constraint-solving techniques. Uppaal also supports diagnostic model-checking providing diagnostic information in case verification of a particular real-time systems fails. The current version of Uppaal is available on the World Wide Web via the Uppaal home page

A constraint-based approach for specification and verification of real-time systems

1997

We develop a general constraint logic programming (CLP) based framework for specification and verification of real-time systems. Our framework is based on the notion of timed automata that have traditionally been used for specihing real-time systems. In our framework, a user models the ordering of real-time events as the grammar of a language accepted by a timed automata, the real-time constraints on these events are then captured as denotations of the grammar productions specijied by the usel: The grammar can be speciJied as a Definite Clause Grammar (DCG), while the denotations can be speccped in constraint logic. The resulting specijication can hence be regarded as a constraint logic program (CLP), and is executable. Many interesting properties of the real-time system can be verc3ed by posing appropriate queries to this CLP program. A major advantage of our approach is that it is constructive in nature, i.e., it can be used for computing the conditions under which a property will holdfor a given real-time system. Our framework also suggests new types of formalisms that we call Constraint Automata and Timed Push-down Automata.

Modeling and verifying real-time properties of reactive systems

Proceedings of the IEEE International Conference on Engineering of Complex Computer Systems, ICECCS, 2013

SPACE is a model-driven engineering technique for reactive distributed systems. It enables to develop system models from reusable building blocks, formal analysis by model checking as well as automated transformation to executable code. In this paper, we describe an extension of the SPACE formalism which allows to model and verify also real-time behavior. In particular, one specifies real-time constraints in the interface descriptions of the building blocks, so-called Real-Time External State-Machines (RTESMs). The RTESMs are translated to guards, clocks and invariants of Timed Automata which can be analyzed by means of the model checker UPPAAL. The approach is explained by a component protecting an electrical motor controller system against overspeed. In particular, we prove that by keeping certain maximum response times, this system guarantees that the speed of the motor stays within certain limits.

Verification of Durational Action Timed Automata using UPPAAL

International Journal of Computer Applications, 2012

The increasing complexity of software is incessant, this phenomenon is even more accentuated when temporal aspects are introduced, hence the need for rigorous verification methods. The main purpose of this paper is to propose a quantitative verification approach based on model checking. Their properties are expressed in TCTL (Timed Computation Tree Logic) on real-time systems. The system behavior is expressed by temporal labeled systems; namely Durational Action Timed Automata model (DATA* model). This model supports the expression of the parallel behavior, the temporal and structural non-atomicity of actions and urgency. Our approach is to interpret the behavior described by DATA* to Timed Safety Automata. The environment UPPAAL allows us verifying quantitative temporal properties, especially the bounded liveliness.

A process algebraic framework for specification and validation of real-time systems

Formal Aspects of Computing, 2009

Following the trend to combine techniques to cover several facets of the development of modern systems, an integration of Z and CSP, called Circus , has been proposed as a refinement language; its relational model, based on the unifying theories of programming (UTP), justifies refinement in the context of both Z and CSP. In this paper, we introduce Circus Time , a timed extension of Circus , and present a new UTP time theory, which we use to give semantics to Circus Time and to validate some of its laws. In addition, we provide a framework for validation of timed programs based on FDR, the CSP model-checker. In this technique, a syntactic transformation strategy is used to split a timed program into two parallel components: an untimed program that uses timer events, and a collection of timers. We show that, with the timer events, it is possible to reason about time properties in the untimed language, and so, using FDR. Soundness is established using a Galois connection between the u...

Compiling real-time specifications into extended automata

IEEE Transactions on Software Engineering, 1992

We propose a method for the implementation and analysis of real-time systems, based on the compilation of specications into extended automata. Such a method has been already adopted for the so called \synchronous" real-time programming languages.

TPAP: an Algebra of Preemptive Processes for Verifying Real-Time Systems with Shared Resources

Electronic Notes in Theoretical Computer Science, 2002

This paper describes a timed process algebra called TPAP. The aim of this algebra is to allow the modelisation of real time embedded processes sharing common resources, and which are sensitive to communication delays and scheduling strategies. Timed broadcasting and process preemption by interruption events are the two main fundamental notions of the algebra. They allow description of schedulers and asynchronous communication mediums, thus which can be taken into account when verifying the real time behaviour of the global system. We first present the process algebra and discuss its properties. A case study from the avionics area is then developed using TPAP, and formally verified by translation into the UPPAAL model checker.

Simulation and formal verification of real time systems: A case study

International Conference on Informatics in Control, Automation and Robotics, 2007

This paper presents and discusses a case study that applies techniques of simulation together with techniques of formal verification. A new approach in the plant modelling for formal verification of timed systems is presented. The modelling of the plant was performed by using the object-oriented language Modelica with the library for hierarchical state machines StateGraph and the simulation results were used as input for the formal verification tasks, using the model checker UPPAAL. It is presented, in a more detailed way, the part of this work that is related to the plant simulation.

Timed behavior trees and their application to verifying real-time systems

… Conference, 2007. ASWEC …, 2007

Behavior Trees (BTs) are a graphical notation used for formalising functional requirements and have been successfully applied to several case studies. However, the notation currently does not support the concept of time and consequently its application is limited to non-real-time systems.