A Novel CNTFET-based Ternary Full Adder (original) (raw)

Low‐power consumption ternary full adder based on CNTFET

IET Circuits, Devices & Systems, 2016

This paper presents low power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the carbon nanotubes, the threshold voltage simple control is the best properties to implement ternary logic circuits. Low complexity, low power consumption and low power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carrygeneration unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, final proposed TFA has reduced the power consumption significantly and results in 86.92 % and 97% reductions in terms of the PDP in comparison with two recent proposed designs. IET Review Copy Only IET Circuits, Devices & Systems This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication in an issue of the journal. To cite the paper please use the doi provided on the Digital Library page.

Two Efficient Ternary Adder Designs Based On CNFET Technology

Journal of Computer and Knowledge Engineering, 2021

Full adder is one of the essential circuits among the various processing elements used in VLSI and other technologies circuits, because they are mainly employed in other arithmetic circuits, such as multi-digit adders, subtractors, and multipliers. This paper proposes two efficient ternary full adders based on Carbon Nanotube Field-Effect Transistor (CNFET) technology. Using the adjustable nanotube diameter in CNFETs, these adders utilize arbitrary threshold voltages so that arithmetic operations can be performed with a radix of 3. For performance analysis, the proposed adder circuits are simulated in HSPICE with 32nm CNFET technology. In these simulations, different inputs are applied at different frequencies with different load capacitances placed at the output. Simulation results have shown that the proposed adders not only improve the speed, power consumption, and Power Delay Product (PDP) of the existing state-of-the-art designs but also improve the design complexity by reducing the number of transistors contained within the circuit.

High performance ternary adder using CNTFET

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016

Ternary logic is a promising alternative to the conventional binary logic in VLSI design as it provides the advantages of reduced interconnects, higher operating speeds and smaller chip area. This paper presents a pair of circuits for implementing a ternary half adder using carbon nanotube field effect transistors (CNTFETs). The proposed designs combine both futuristic ternary and conventional binary logic design approach. One of the proposed circuits for ternary to binary decoder, simplifies further circuit implementation and provides excellent delay and power advantages in data path circuit such as adder. These circuits have been extensively simulated using HSPICE to obtain power, delay and power delay product. The circuit performances are compared with alternative designs reported in recent literature. One of the proposed ternary adders has been demonstrated power, power delay product improvement up to 63% and 66% respectively, with lesser transistor count. So, the use of these half adders in complex arithmetic circuits will be advantageous.

High Performance CNFET-based Ternary Full Adders

IETE Journal of Research

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET technology. The proposed methods are simulated at different conditions such as different supply voltages, different temperature and operational frequencies. Simulation results show that the proposed designs are faster than the state of the art CNFET based ternary full adders.

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

Frontiers of Information Technology & Electronic Engineering, 2017

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.

A low-power high speed full adder cell using carbon nanotube field effect transistors

The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS), 2023

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

Energy Efficient CNTFET Based Full Adder Using Hybrid Logic

—Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated (VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall performance of electronic devices. Due to unique mechanical and electrical characteristics, carbon nanotube field effect transistors (CNTFET) are found to be the most suitable alternative for metal oxide field effect transistor (MOSFET). CNTFET transistor utilizes carbon nanotube (CNT) in the channel region. In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology is presented. Two input full swing XOR gate is designed using 4 transistors which is further used to generate Sum and Carry output signals with the help of Gate-Diffusion-Input (GDI) Technique thus reducing the number of transistors involved. Proposed design simulated in Cadence Virtuoso with 32nm CNTFET technology and results is better design as compared to existing circuits in terms of Power, Delay, Power-Delay-Product (PDP), Energy Consumption and Energy-Delay-Product (EDP).

Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology

Circuits, Systems, and Signal Processing, 2019

This article presents the low-power ternary arithmetic logic unit (ALU) design in carbon nanotube field-effect transistor (CNFET) technology. CNFET unique characteristic of geometry-dependent threshold voltage is employed in the multi-valued logic design. The ternary logic benefit of reduced circuit overhead is exploited by embedding multiple modules within a block. The existence of symmetric literals among various single shift and dual shift operators in addition and subtraction operations results in the optimized realization of adder/subtractor modules. The proposed design is based on the notion of multiplexing either arithmetic, logical or miscellaneous operations, depending upon the status of input selection trits. The results obtained by the synopsis HSPICE simulator with the Stanford 32 nm CNFET technology illustrate that the proposed processing modules outperform their counterparts in terms of power consumption, energy consumption and device count. The proposed methodology leads to saving in power consumption and energy consumption (PDP) of 62% and 58%, respectively, on the benchmark circuit of the ALU [full adder/subtractor (FAS)]. Furthermore, for the 2-trit multiplier design, the enhanced performance at the architecture and circuit level is achieved through the optimized designs of various adder and multiplier circuits. Keywords Carbon nanotube field-effect transistor (CNFET) • Multi-valued logic design • Ternary ALU • Nano-technology • Low power B Trapti Sharma

Ternary Logic Circuits Using Cntfet: A Brief Review

International Journal of Engineering Applied Sciences and Technology, 2020

A brief review about carbon nanotube is presented at first, followed by nnnnnna brief review of ternary logic and then finally some of the ternary logic circuit built with carbon nanotube field effect transistor (CNTFET) are discussed. Recent progress in ternary logic circuit proposed by using CNTFET as basic building block is discussed in this paper. Complementary CNTFET designs are used to build ternary logic circuits just like Complementary CMOS designs. MVL has gained its popularity as binary logic circuits are reaching its limitations. Different CNTFET Ternary logic circuits like half adder (HA), full adder (FA) and multiplier circuits are studied and a brief review is presented in this paper about how different designs and different methodologies are proposed to achieve high performance, low power consuming and also with less delay.

An applicable high-efficient CNTFET-based full adder cell for practical environments

Full adder is among the most practical logic blocks. It is the main arithmetical component of all digital systems. This paper presents the novel design of a high-speed and high-efficient full adder cell which is on the basis of low-complex passtransistor logic. Using carbon nanotube field effect transistors, formation of transmission gates are not required and the usage of extra transistors is avoided. It benefits from ultra high computational speed which makes it ideal for high-speed and high-frequency applications. It could be employed in portable devices as it consumes very low power. It has also the advantage of working reliably in spite of fabrication imperfections. Simulations are carried out using Synopsys HSPICE in a realistic test bench and other various strict conditions. Simulation results demonstrate higher efficiency with respect to other conventional and state-of-the-art CNTFET and MOSFET implementations.