Energy Efficient CNTFET Based Full Adder Using Hybrid Logic (original) (raw)
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A low-power high speed full adder cell using carbon nanotube field effect transistors
The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS), 2023
The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.
An applicable high-efficient CNTFET-based full adder cell for practical environments
Full adder is among the most practical logic blocks. It is the main arithmetical component of all digital systems. This paper presents the novel design of a high-speed and high-efficient full adder cell which is on the basis of low-complex passtransistor logic. Using carbon nanotube field effect transistors, formation of transmission gates are not required and the usage of extra transistors is avoided. It benefits from ultra high computational speed which makes it ideal for high-speed and high-frequency applications. It could be employed in portable devices as it consumes very low power. It has also the advantage of working reliably in spite of fabrication imperfections. Simulations are carried out using Synopsys HSPICE in a realistic test bench and other various strict conditions. Simulation results demonstrate higher efficiency with respect to other conventional and state-of-the-art CNTFET and MOSFET implementations.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology
International Journal of VLSI Design & Communication Systems, 2014
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
A low-voltage and energy-efficient full adder cell based on carbon nanotube technology
2010
Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT (Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP (Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages. Citation: Keivan Navi, Rabe'e Sharifi Rad, Mohammad Hossein Moaiyeri and Amir Momeni, "A low-voltage and energy-efficient full adder cell based on carbon nanotube technology", Nano-Micro Lett. 2, 114-120 (2010). doi:10.5101/ nml.v2i2.p114-120 Scaling down the feature size of MOSFET devices in nanometer, leads to serious challenges, such as short channel effects, very high leakage power consumption and large parametric variations. Due to these limitations researchers become eager to work toward new emerging technologies such as Quantum Automata (QCA) [1], Nanowire transistors [2] and Carbon Nanotube Field Effect Transistors (CNFET) [3]. By the mentioned problems of nanoscale CMOS technology, which makes it unsuitable for low-power and low-voltage applications in the near future, these nano-devices could replace the conventional silicon MOSFET in the time to come. However, due to the similarities between the infrastructure and functionality of the conventional MOSFET devices with CNFETs and also because of the ballistic operation of CNFETs, it could be more promising and achievable, compared to other nano-devices. Recently some efforts have been done for designing circuits based on CNFET such as multiple valued logic circuits [4,5], arithmetic circuits [6] and so on, taking
Performance Investigation of a full adder using CNTFET Technology
—The integration of digital circuits has a closer relation with the scaling down of silicon technology. But continuous scaling down of the CMOS devices leads to the vicious effects as short channel effects. Accordingly, the thirst for exploring the novel technique to replace silicon technology has risen. The carbon nanotube FET (CNTFET) is one of the emerging technologies because of its principal features. Many kinds of digital circuits such as standard logic cells designed, and the results prove progress concerning power, delay, and area. In this paper, a novel 4-bit full adder circuit designed and simulated using the HSPICE tool using the 32-nm SPICE model for the CNTFET. The proposed adder circuit gives the better results and the device compared to the FinFET technology. Index Terms—4-bit full adder, CNTFET, challenges in CNT, chirality vector, parametric analysis, device simulation, power delay product, FinFET, MVL, and CMOS.
Design and Analysis of a New Carbon Nanotube Full Adder Cell
Journal of Nanomaterials, 2011
A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.
An Energy-Efficient Full Adder Cell Using CNFET Technology
IEICE Transactions on Electronics, 2012
The reduction in the gate length of the current devices to 65 nm causes their I-V characteristics to depart from the traditional MOS-FETs. As a result, manufacturing of new efficient devices in nanoscale is inevitable. The fundamental properties of the metallic and semi-conducting carbon Nanotubes (CNTs) make them alternatives to the conventional silicon-based devices. In this paper an ultra high-speed and energy-efficient full adder is proposed, using Carbon Nanotube Field Effect Transistor (CN-FET) in nanoscale. Extensive simulation results using HSPICE are reported to show that the proposed adder consumes lower power, and is faster compared to the previous adders.
CNTFET Full-Adders for Energy-Efficient Arithmetic Applications
2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2015
In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm for CNTFETs, the proposed circuits enjoy full swing in all outputs and internal nodes, structural symmetry, reduced power-delay product (PDP) and energy-delay product (EDP), fairly balanced outputs and high driving capability. The state of the art includes both bulk CMOS and CNTFET technologies. The simulation results exhibit an average PDP and EDP improvement of 9-98% and 55-99% respectively compared with the referenced FAs. All HSPICE simulations were performed on 32nm CNTFET and CMOS process technologies.
Low‐power consumption ternary full adder based on CNTFET
IET Circuits, Devices & Systems, 2016
This paper presents low power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the carbon nanotubes, the threshold voltage simple control is the best properties to implement ternary logic circuits. Low complexity, low power consumption and low power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carrygeneration unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, final proposed TFA has reduced the power consumption significantly and results in 86.92 % and 97% reductions in terms of the PDP in comparison with two recent proposed designs. IET Review Copy Only IET Circuits, Devices & Systems This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication in an issue of the journal. To cite the paper please use the doi provided on the Digital Library page.