A novel fast online placement algorithm on 2D partially reconfigurable devices (original) (raw)
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Optimized Placement Approach on Reconfigurable FPGA
International Journal of Modeling and Optimization
Adaptive systems based on Field-Programmable Gate Array (FPGA) architectures can benefit from the high degree of flexibility offered by Dynamic Partial Reconfiguration (DPR). In DPR, hardware modules composing an application can be allocated on demand or depending on a dynamically changing system. However, founders DPR tools are limited in functionality because it does not support an automatic placement , and require a manual inputs from the design. Manual placement not allows an efficient placement. The placement step represents a critical step in DPR flow on FPGA. It is highly impact routability, timing and density, hence performance of the system. In this paper, we present a novel placement algorithm to address these constraints by offering minimal fragmentation that minimizes resource utilization and reduces the total wirelength. The selection of the Partial Reconfigurable Region (PRR) is based on the shapes, location and communication with others. The proposed approach has been experimentally evaluated with a case study. Experimental results show the effectiveness of the proposed algorithm in the terms of exploration area and communication cost.
An Algorithm for Dynamically Reconfigurable FPGA Placement
International Conference on Computer Design, 2001
In this paper, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2%, 27.0%, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method
Fast online task placement on FPGAs: free space partitioning and 2D-hashing
Proceedings International Parallel and Distributed Processing Symposium, 2003
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reconfigurable resource which leads to the concept of a reconfigurable operating system. A major aspect of such an operating system is task placement. Online placement methods are required that achieve a high placement quality and lead to efficient implementations.
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems, 2002
In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
ACM Transactions on …, 2010
The aim of this article is to describe a complete partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs and considering communication infrastruc-ture feasibility. This article proposes a novel approach for resource-and ...
Online Modules Placement Algorithm on Partially Reconfigurable Device for Area Optimization
In this paper we propose a new method of modules placement on the partially reconfigurable device. The main aim of our method is to optimize the area occupation of the device when placing the modules. The key word of our algorithm is the not consideration of the heights and the widths of modules, like former algorithms. In fact, our algorithm uses the size of modules; next it computes the heights and the widths of modules, and after that it places them on the device while optimization the area occupation. Moreover, most of existing algorithms do not evaluate their algorithms on real hardware device; we do experimentations of our tasks on a real FPGA Virtex-5. Results show that our algorithm achieves better placement quality in term of area occupation and faster in term of run time compared to existing approaches.
Microprocessors and Microsystems, 2009
Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadline-constrained task placement algorithm for minimizing area fragmentation on the FPGA by using an area fragmentation metric that takes into account probability distribution of sizes of future task arrivals as well as the time axis. The techniques presented in this paper are useful in an operating system for runtime reconfigurable FPGAs to manage the HW resources on the FPGA when HW tasks that arrive and finish dynamically at runtime.
Fast FPGA Placement using Space-filling Curve
2005
In this paper, we propose a placement method for islandstyle FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of our method show 55% improvement in cost, when compared to random initial placement of the popular tool VPR. The solutions thus obtained require 44.5% fewer moves during final iterative refinement by ultra-low temperature simulated annealing, whereas the quality of solution is on the average 0.1% better. This establishes the utility of the method for fast reconfiguration of FPGA based co-processors.
SELECTIVE FITTING STRATEGY BASED REAL TIME PLACEMENT ALGORITHM FOR DYNAMICALLY RECONFIGURABLE FPGAs
Engineers in the field of Advanced computing paradigm struggles to satisfy the demand of high performance applications in terms of speed such as image processing, embedded computing ,video stream processing etc.,. Providing high speed in terms of truly multitasking of reconfigurable computing devices such as FPGAs acts as suitable computing platform for such applications. Two main problems in FPGA to fulfil the requirement are scheduling and placement of incoming hardware tasks. Scheduling and placement are the two process that depends on each other. Improper scheduling affects the placement performance. To the above two things, one more factor called fragmentation related closely that affects performance of FPGAs during placement. The performance metric used in this paper is task rejection ratio. Effective placement algorithm results minimum task rejection ratio. In this paper, we address the problem of real time scheduling and placement of hardware tasks by considering the factor called fragmentation in the objective to minimize the task rejection ratio. We developed an Selective fitting strategy based algorithm and simulation is carried out. Results are compared with basic placement fitting strategy such as first fit, best fit and worst fit. Our algorithm shows better performance in term of task rejection ratio.
2010
Few of the benefits of exploiting partially reconfigurable devices are power consumption reduction, cost reduction, and customized performance improvement. To obtain these benefits, one main problem needs to be solved is the task scheduling and placement. Existing algorithms tend to allocate tasks at positions where can block future tasks to be scheduled earlier denoted as "blocking-effect". To tackle this effect, a novel 3D total contiguous surface (3DTCS) heuristic is proposed for equipping our scheduling and placement algorithm with blockingawareness. The proposed algorithm is evaluated with both synthetic and real workloads (e.g. MDTC, matrix multiplication, hamming code, sorting, FIR, ADPCM, etc). The proposed algorithm not only has better scheduling and placement quality but also has shorter algorithm execution time compared to existing algorithms.