SRAM Cell Stability: A Dynamic Perspective (original) (raw)
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SRAM dynamic stability: Theory, variability and analysis
2008 IEEE/ACM International Conference on Computer-Aided Design, 2008
Technology scaling in sub-100nm regime has significantly shrunk the SRAM stability margins in data retention, read and write operations. Conventional static noise margins (SNMs) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art SRAMs with shrinking access time and/or advanced dynamic read-write-assist circuits. Using the insights gained from rigorous nonlinear system theory, we define the much needed SRAM dynamic noise margins (DNMs). The newly defined DNMs not only capture key SRAM nonlinear dynamical characteristics but also provide valuable design insights. Furthermore, we show how system theory can be exploited to develop CAD algorithms that can analyze SRAM dynamic stability characteristics three orders of magnitude faster than a brute-force approach while maintaining SPICE-level accuracy. We also demonstrate a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to three orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations.
Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
In energy-constrained applications, SRAM systems operating in the subthreshold region are often deployed to reduce power consumption. Subthreshold SRAM designs, however, confront numerous challenges such as susceptibility to process variation and reduced on-off current ratio. Statistical modeling of the variation in cell stability is critical in SRAM design, especially for designs operating in the subthreshold region where the process and temperature variations are the most pronounced. In this paper, statistical models for estimating static noise margins (SNM) of SRAM cells are built from the perspective of a shifted voltage transfer characteristic. Read (Hold) SNM of a subthreshold 8T cell is analyzed. It is shown that the distribution of a single-sided Read SNM is a weighted sum of several normal distributions instead of a regular Gaussian distribution. The proposed statistical model is verified with simulation results in 65 nm technology. Furthermore, to mitigate performance and yield degradation, an adaptive body biasing circuit is developed. It is demonstrated through simulation that, with a negligible area and power overhead, the proposed circuit achieves a 15% improvement in the worst-case Read SNM.
Analytical Modeling of SRAM Dynamic Stability
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
In this paper, for the first time, a theory for evaluating dynamic noise margins of SRAM cells is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closed-form expression. The key innovation involves using the methods of nonlinear system theory in developing the model. It is shown that when a transient noise of given magnitude affects a sensitive node of a cell, the bi-stable, feedback-driven nature of the cell determines whether the noise will be suppressed or will evolve to eventually flip state. The specific formal and quantitative result is a closed-form expression that can be used to predict whether a cell flip will occur for a noise signal with specific characteristics, and for a given SRAM cell design. Experiments show excellent match between the analytical prediction and the SPICE simulation results.
Static Noise Margin Analysis of Various SRAM Topologies
ijetch.org
In the present time, great emphasis has been given to the design of low-power and high performance memory circuits. As an SRAM is a critical component in both high-performance processors and hand-held portable devices. So the ever-increasing levels of on-chip integration of SRAM, offers serious design challenges in terms of power requirement and cell stability. There is a significant increase in the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide thickness. In order to minimize the leakage current, the supply voltage is reduced drastically which reduces the threshold voltage of the cell.This reduces the threshold voltage of the cell which results in reduction of the Static Noise Margin (SNM) of the cell and affect the data stability of the cell, seriously. In this work, the solutions for theses two problems, in the conventional 6T SRAM Cell has been explored.
Read stability and Write ability analysis of different SRAM cell structures
2014
SRAM cell read stability and write-ability is major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and VDD scaling. This paper analyzes the read stability and write ability of 6T, 8T, 9T SRAM cell structures. SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation. This paper represents the simulation of three SRAM cell topologies and their comparative analysis on the basis of read noise margin (RNM), write noise margin (WNM). Both 8T SRAM cell and 9T SRAM cell provides higher read noise margin as compared to 6T SRAM cell. Although the size of 9T SRAM cell is higher than that of the 8T SRAM cell but it provides higher write stability. In this paper we propose a methodology to characterize the DC noise margin of 6T, 8T and 9T SRAM. All simulations of the SRAM cell have been carried out in 130nm CMOS technology.
Static-Noise Margin Analysis during Read Operation of 6T SRAM Cells
SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word-and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing current leakage, as opposed to current methods that improve cell read stability at the cost of leakage increase.
In this paper we introduce Noise (the Static Noise present in 7T SRAM cell) effect the stability of cell. Actually SNM is present in SRAM cell which is effect the stability in read operation of the 7T SRAM cells. SRAM cell stability analysis is a based on Static Noise Margin (SNM) investigation when in read mode, although many memory errors may occur during read operations. So that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word-and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing word line voltage.
A black box method for stability analysis of arbitrary SRAM cell structures
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
Static noise margin analysis using butterfly curves has traditionally played a leading role in the sizing and optimization of SRAM cell structures. Heightened variability and reduced supply voltages have resulted in increased attention being paid to new methods for characterizing dynamic robustness. In this work, a technique based on vector field analysis is presented for quickly extracting both static and dynamic stability characteristics of arbitrary SRAM topologies. It is shown that the traditional butterfly curve simulation for 6T cells is actually a special case of the proposed method. The proposed technique not only allows for standard SNM "smallest-square" measurements, but also enables tracing of the state-space separatrix, an operation critical for quantifying dynamic stability. It is established via importance sampling that cell characterization using a combination of both separatrix tracing and butterfly SNM measurements is significantly more correlated to cell failure rates then using SNM measurements alone. The presented technique is demonstrated to be thousands of times faster than the brute force transient approach and can be implemented with widely available, standard design tools.
A Subthreshold Symmetric SRAM Cell With High Read Stability
IEEE Transactions on Circuits and Systems II: Express Briefs, 2014
This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition, the read and write noise margins of the conventional six-transistor (6T) cell are 18 and 27 mV, respectively. The cell area is 1.57× the conventional 6T SRAM cell area in 45-nm design rules.