Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint (original) (raw)
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Investigation on flip chip solder joint fatigue with cure-dependent underfill properties
IEEE Transactions on Components and Packaging Technologies, 2003
A cure-dependent viscoelastic constitutive relation is applied to describe the curing process of epoxy underfill in flip chip on board (FCOB). The chemical shrinkage of the epoxy underfill during the curing process is applied via incremental initial strains. Thus, the stress and strain build-up, caused by the simultaneous increase in stiffness and shrinkage during the curing process, are simulated. Accelerated fatigue experiments with thermal cycles from 55 C to 80 C are carried out for a specially designed flip chip configuration. Based on the obtained curing induced initial stress and strain fields, thermo-mechanical predictions are presented for the test carriers. The solder bumps are modeled with temperature dependent visco-plastic properties. A combination of a Coffin-Manson based fatigue relation and a creep fatigue model is used as fatigue failure criterion. The results show that the finite element method (FEM)-based fatigue life predictions match better with the experimental results, if the curing induced initial stress state is taken into account. The effect of cure-induced hydrostatic stress is qualitatively investigated by using a modified energy partitioning damage model with a correction factor in the creep damage formulation to take into account the effect of the hydrostatic stress.
IEEE Transactions on Components and Packaging Technologies, 2008
In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 C-240 C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill. Index Terms-finite-element analysis, flip chip, parametric study, phase change, Pb-free solder, strain energy release rate. I. INTRODUCTION S INCE the Pb-based solders have many advantages in cost, wetting characteristics, and availability in various melting temperatures, they have been widely used to provide electrical interconnection in electronics packaging. However, the use of Pb-based solders is being prohibited by the environmental regulations. Therefore, many studies have been performed
No-flow underfill flip chip assembly––an experimental and modeling analysis
Microelectronics Reliability, 2002
In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal-mechanical fatigue life of flip chips with no-flow underfill.
Improvement of Board Level Reliability for μBGA Solder Joints Using Underfill
MATERIALS TRANSACTIONS, 2003
The underfilling BGA as an alternative to direct chip attachment for high density packaging technologies have been developed. This paper discusses the thermomechanical and metallurgical effects of underfill material and the resulting improvement in board level reliability for underfilled BGA assemblies. Finite element analysis (FEA) models were developed to predict the thermal fatigue life of the solder joints during thermal cycling tests for BGA assemblies without and with underfill material. FEA predicted that the stress concentrated in the solder at the crevice between the solder ball and upper substrate was approximately 60 percent of the stress without underfill. Subsequently, the predicted fatigue life was as much as 10 times higher for the underfilled assemblies. The thermal fatigue failure of BGA solder joints was also investigated experimentally using thermal cycle testing with subsequent solder joint analysis by scanning electron microscope (SEM) and energy dispersive X-ray (EDX). The experiments revealed that solder joint failure was caused by propagation of cracks that initiated in the solder at the upper interface between the solder ball and copper pad. The fatigue life of the underfilled assemblies was about 8 times that of the assemblies without underfill. The results showed that the underfill material can play an important role in improving board level reliability for BGA solder joints in harsh environments.
IEEE Transactions on Electronics Packaging Manufacturing, 2002
Solder bumped Flip Chips on low cost substrates with three different epoxy-based no-clean flux liquid-like no-flow underfills are presented in this study. This paper includes evaluation of three commercial no-flow underfills and characterization of material and process parameters. Important materials and process parameters, such as curing temperature and time, thermal coefficient of expansion, storage modulus, loss modulus, tand, glass transition temperature, moisture uptake, solder reflow, and post curing are discussed in this work. Curing mechanism during reflow of no-flow underfills will be illustrated in this paper and a comparison of noflow underfill and conventional underfill will be also addressed. Also, cross-sections are examined for a better understanding of the effects of these no-flow underfill materials on the interconnects of the Flip Chip assemblies. Shear and thermal-cycling tests and results of these Flip Chip assemblies are reported and analyzed.
ECTC 2011, 2011
We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses pulsed amplitude pressure. A WLUF with 60% (weight) filler was applied by spin coating onto a wafer with Pb-free solder bumps. Following B-stage curing at 90 o C, the thickness was measured to be 20 microns over the solder bump height. In the B-staged state, this WLUF is stable at room temperature for several weeks. After the wafer was diced into chips, a chip was aligned and joined to a substrate with an optimized heating and cooling cycle. This WLUF assembly process has been evaluated using a flip chip test vehicle with 150 micron pitch and 3,300 area array solder bumps. The chip bumps were SnAg solder and the pre-solder on the substrate was SnAgCu. The size of the test chip was 9 x 13 mm and the test substrate was 42.5 x 42.5 mm. The test chip and substrate were designed to allow both two and four wire contact resistance measurements of the electrical interconnect structures. We successfully demonstrated 100% electrically and metallurgically good Pb-free joints. Voids inside the WLUF after flip chip bonding were decreased significantly using the pulsed amplitude pressure, post cure process. Scanning acoustic microscopy (SAM) analysis showed nearly void-free underfill bonding. After JEDEC level three preconditioning, environmental stress testing was completed and included 1000 deep thermal cycles of-55 to 125 o C; 1000 hrs at 85C/85% temperature and humidity; and 1000 hrs of 150 o C high temperature storage. Contact resistance measurements were made at time zero, after preconditioning and every 250 cycles or hours of environmental stress. The contact resistance measurements were stable on all parts. Detailed material and process development, and reliability test results are described in this paper.
Parametric finite element Analysis of solder joint reliability of flip chip on board
… Technology Conference, 1998. Proceedings of 2nd, 1998
Numerous studies have indicated that by encapsulating the solder joint with underfill material, the reliability of flip chip on board (FCOB) assemblies can be effectively enhanced. Typical manufacturing process for FCOB assembly with underfill, however, involves long throughput time and additional equipment sets which are undesirable for high volume manufacturing environments. Hence, desigdprocess simplification if not total elimination of underfill from the conventional FCOB assemblies that can directly result in productivity gain should be considered. A comprehensive parametric finite element analysis has been conducted to assess the feasibility of FCOB structures with partial underfill (i.e. only the peripheral joints are encapsulated with underfill material.) The effects of some critical design parameters such as die size, joint height, joint diameter, joint pitch, printed circuit board (PCB) thickness and material properties of underfill on the solder joint reliability of FCOB structure were investigated in this study. Two-dimensional nonlinear plane strain finite element models of FCOB package are employed. Moire and IR Fizeau interferometry technique are used to measure the thermal deformation of the FCOB for model validation. Elasto-plastic deformation behaviors of solder were simulated under thermal cyclic loading from-55 "C to 125 "C. Maximum effective elastic and plastic strains of the solder joint were calculated and used as the indicator for determining the solder joint reliability of the structures.
Void Formation Study of Flip Chip in Package Using No-Flow Underfill
IEEE Transactions on Electronics Packaging Manufacturing, 2000
The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.
Microelectronics Reliability, 2000
The effect of thermo-mechanical properties of underfill, such as coefficient of thermal expansion (CTE) and stiffness (Young's modulus), on reliability of Flip Chip on Board (FCOB) under thermal cycling stresses is investigated in this study. 3-D and Quasi three-dimensional viscoplastic stress analysis using finite element modeling (FEM) is combined with an energy partitioning (EP) model for creep-fatigue damage accumulation, to predict the fatigue durability for a given thermal cycle. Parametric FEM simulations are performed for five different CTEs and five different stiffnesses of the underfill. The creep work dissipation due to thermal cycling is estimated with quasi 3-D model, while 3-D model are used to estimate the hydrostatic stresses. To minimize the computational effort, the 3-D analysis is conducted only for the extreme values of the two parameters (CTE and stiffness) and the results are interpolated for intermediate values.
Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability
—In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic sub-strate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow under-fill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.