A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology (original) (raw)
Related papers
Analog Integrated Circuits and Signal Processing, 2019
Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work describes such a structure through the use of a novel low offset comparator thereby reducing the non-linearity performance along with significant improvement in energy-delay metric. A high speed control circuitry is introduced to improve the overall frequency of operation of SAR-ADC minimizing its speed limitation. Capacitive based digital-to-analog converter is used that switches in alternate cycles to reduce the static power dissipation. The ADC architecture is designed in 45-nm CMOS technology at layout of 0:0139 mm 2. The extracted results show that the proposed design is a reliable framework to ascertain the effectiveness of SAR-ADC with a faster performance. The results demonstrate an improvement of 47.75% in figure-of-merit. SNDR and SFDR are found to be 57.2 dB and 61.4 dB respectively at input frequency of 10 MHz. The sampling frequency is taken as 1 GHz with a power supply of 1 V.
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology
2017
In this paper, a new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on capacitor merged technique is presented. The main goal of the proposed idea is to achieve high-resolution and high-speed SAR ADC, simultaneously. It is noteworthy that, exerting the suggested method, the total capacitance and the ratio of the MSB and LSB capacitors are decreased; as a result, the speed and accuracy of the ADC are increased reliably. Therefore, applying the proposed idea, it is reliable that to attain a 12-bit resolution ADC at 76MS/s sampling rate. Furthermore, the power consumption of the proposed ADC is 694µW with the power supply of 1.8 volts correspondingly. The proposed postlayout SAR ADC structure is simulated in all process corner conditions and different temperatures of-50℃ to +50℃, and performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.
Design and Implementation of 10 Bit, 2MS/s Split SAR ADC Using 0.18um CMOS Technology
International Journal of VLSI Design & Communication Systems, 2015
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter (DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is 96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimized architecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy of the components, which improves the performance of SAR ADC. Comparator constructed from resistances, capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS
Analog Integrated Circuits and Signal Processing, 2014
The conventional binary weighted array successive approximation register (SAR) analog-to-digital converter (ADC) is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/ conversion-step, even if it requires extra effort to design and simulate full custom fF or sub-fF capacitors. This paper presents the design and the optimization of an asynchronous fully-differential SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. The 10-bit converter prototype has been fabricated in a standard 0.13-lm CMOS technology. At a 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it's the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an active area of only 0.045 mm 2 .
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 265 m 2 .
A 1.2V 8 Bit Sar Analog to Digital Converter in 90NM Cmos
Successive approximation register (SAR) analog to digital converters are widely utilized for low speed and low power applications. This paper shows a configuration of a 8 bit SAR ADC which uses monotonic capacitor switching strategy. This switching plan lessens the total capacitance in the DAC circuit which by implication prompts reduction in power consumption. Dynamic latch comparator with stack approach is utilized among the key building modules of SAR ADC, the use of this comparator lessens the leakage current in the circuit. The designed 8 bit SAR ADC is executed by utilizing 90nm CMOS technology and works at supply voltage of 1.2V. The planned SAR analog to digital converter consumes 93.01µW power. Keywords: Analog to digital converter (ADC), capacitive network, digital to analog converter (DAC), Successive approximation register(SAR)
A low power 12-bit 1MSps SAR ADC with capacitor array network
This paper proposes a low power 12-bit 1MSps SAR ADC (Successive Approximation Register Analog-to-Digital Converter) with capacitor array network for SoC (System-on-Chip). The proposed circuit is designed using Magnachip/SK Hynix 0.18 μm CMOS 1Poly-6Metal process, and it is powered by 1.5 supply voltage. The proposed circuit in this paper showed high SNDR (Signal-to-Noise Distortion Ratio) of 71.18dB, and excellent ENOB (effective bit number ofbits) of 11.53-bit as compared to conventional research results. The designed circuit also showed very low power consumption of 1.95mW
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
Electronics, 2020
A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, ...
A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Analog Integrated Circuits and Signal Processing, 2021
During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15....
— A low power (0.4-09V) 2-Bit/Step successive approximation register (SAR) analog to digital converter (ADC) is conferred. A 2-Bit/Step operation technique is proposed which implementing a dynamic threshold configuring comparator instead of number of digital to analog converters (DACs). Area and power is reduced by successively activated comparators. Here the second comparator is activated reflecting the preceding comparator " s results. Because the second comparator threshold is configured dynamically for every cycle, only two comparators are required instead of three. By successively activating the comparators, the number of DAC settling is halved, so the power and area overhead is very small and the performance will be increased. The proposed ADC was implemented in a 90nm technology achieved a gain of 35.4 db, power of 0.89 μw and the conversion time of 0.32ns with a supply voltage of 0.4v. The total core area of this ADC is 7.74 μm 2 .