A compact model of silicon-based nanowire MOSFETs for circuit simulation and design (original) (raw)
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A Compact Model of Silicon-Based Nanowire Field Effect Transistor for Circuit Simulation and Design
ArXiv, 2014
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the performance limits and scaling potentials of SNWTs and to address the SNWT design issues. The computer based simulations carried out are essentially based on DFT using NEGF formalism. A silicon nanowire has been modeled as PN diode (Zener Diode), PIN diode, PIP & NIN diode configurations by selectively doping the nanowire and simulated by biasing one end of the nanowire to ground and sweeping ...
A Simulation Study of Silicon Nanowire Field Effect Transistors (FETs)
2007
Silicon planar MOSFETs are approaching their scaling limits. New device designs are being explored to replace the existing planar technology. Among the possible new device designs are Double Gate (DG) FETs, FinFETs, Tri-Gate FETs and Omega-Gate FETs. The Silicon Nanowire Gate All Around (GAA) FET stands out as one of the
Silicon, 2022
In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (Φ S), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (N d) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator.
An Analytical Compact Circuit Model for Nanowire FET
IEEE Transactions on Electron Devices, 2007
In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and driftdiffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for current-voltage (I-V) and capacitance-voltage characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of an NWFET device. Results show a close match of the model with measured data.
Journal of NanoScience, NanoEngineering & Applications, ISSN: 2231-1777(online), ISSN: 2321-5194(print) Volume 5, Issue 2, 2015
Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at the end of the paper justifies the theory of nanowire FETs to carry forward the downscaling of MOSFETs in the sub-10 nm regime.
International Journal of the Physical Sciences, 2012
In this paper, electrical characteristics of the double gate metal oxide semiconductor field effect transistor (DG MOSFET) and that of gate all around silicon nanowire transistor (GAA SNWT) have been investigated. We have evaluated the variations of the threshold voltage, the subthreshold slope, draininduced barrier lowering, ON and OFF state currents when channel length decreases. Quantum mechanical transport approach based on non-equilibrium Green's function method (NEGF) has been performed in the frame work of effective mass theory with taking into account exchange-correlation effects. Its simulation consists of solutions of the three dimensional Poisson's equation, two dimensional Schrodinger equation on the cross section plane, and also transport equation. We have shown that for lengths smaller than 15 nm, short channel effects dominate. When the dimensions become smaller, interelectronic distance decreases and the interaction between electrons and also exchange correlation effects increase. We have also demonstrated that short channel effects are decreased using the device which has a good control of gate.
An Analytic Model for Nanowire MOSFETs With Ge/Si Core/Shell Structure
IEEE Transactions on Electron Devices, 2000
An analytic model for the nanowire MOSFETs (NWFETs) with Ge/Si core/shell structure is developed in this paper. The analytical expressions of electrostatic potential and charges of this device are derived from classical device physics under the gradual channel approximation. Then, a drift-diffusion (DD) mechanism-based drain current model is obtained and verified by comparisons with the numerical simulation results. By modifying the intrinsic carrier concentration under 2-D confinement, quantum-mechanical effect is also taken into account approximately, and then, a ballistic current model is developed to study the impact of quantum-mechanical effect on the device characteristics. The performances of Ge/Si core/shell NWFETs are analyzed, and significant characteristics are demonstrated, in detail, by the proposed model. The presented analytic model may provide a base for device scientists and circuit engineers to understand the device physics and further develop a compact model of the NWFETs with Ge/Si core/shell heterostructure for circuit design and simulation. Index Terms-Analytic model, ballistic transport, core/shell, Ge/Si heterojunction, nanowire MOSFETs (NWFETs), Poisson-Boltzmann equation, quantum-mechanical effect.
Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs
Active and Passive Electronic Components, 2013
An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.
2007
In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and drift-diffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for I-V and C-V characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of a NWFET device. Results show a close match of the model with measured data.