InGaAs-InP DHBTs for increased digital IC bandwidth having a 391-GHz f/sub /spl tau// and 505-GHz f/sub max/ (original) (raw)
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High-speed small-scale InGaP/GaAs HBT technology and its application to integrated circuits
IEEE Transactions on Electron Devices, 2001
We have developed the advanced performance, smallscale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO 2 in the extrinsic collector. The base-collector capacitance BC was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO 2 , reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO 2 region by 50% compared to our previous devices. The cutoff frequency T of 156 GHz and the maximum oscillation frequency max of 255 GHz were obtained at a collector current C of 3.5 mA for the HBT with an emitter size E of 0.5 4.5 m 2 , and T of 114 GHz and max of 230 GHz were obtained at C of 0.9 mA for the HBT with E of 0.25 1.5 m 2 . We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications.
Submicron InP-based HBTs for Ultra-high Frequency Amplifiers
International Journal of High Speed Electronics and Systems, 2003
Transistor bandwidths are approaching terahertz frequencies. Paramount to high speed transistor operation is submicron device scaling. High bandwidths are obtained with heterojunction bipolar transistors by thinning the base and collector layers, increasing emitter current density, decreasing emitter contact resistivity, and reducing the emitter and collector junction widths. In mesa HBTs, minimum dimensions required for the base contact impose a minimum width for the collector junction, frustrating device scaling. We have fabricated HBTs with narrow collector junctions using a substrate transfer process. HBTs with submicron collector junctions exhibit extremely high fmaxand high gains in mm-wave ICs. Transferred-substrate HBTs have obtained record 21 dB unilateral power gain at 100 GHz. Recently-fabricated devices have shown unbounded unilateral power gain from 40-110 GHz, and fmaxcannot be extrapolated from measuremente. However, these devices exhibited high power gains at 220 GHz...
Ultra high speed InP heterojunction bipolar transistors
This thesis deals with the development of high speed InP mesa HBT's with power gain cutoff frequencies up to and above 300 GHz, with high current density and low collector discharging times. Key developments are Pd-based base ohmics yielding base contact resistances as low as 10 Ωµm 2 , base-collector grades to enable to use of InP in the collector, and an increase in the maximum current density through collector design and thermal optimization. HBT's with a linear doping gradient in the base are for the first time reported and compared to HBT's with a bandgap graded base. The effect of degenerate base doping is simulated, as well as the base transit time. Key results include a DHBT with a 215 nm thick collector and an f τ = 280 GHz, and f max =400 GHz. This represents the highest f max reported for a mesa HBT. Results also include a DHBT with a 150 nm thick collector and an f τ = 300 GHz, and f max =280 GHz. The maximum operating current density has been increased to above 10 mAµm while maintaining f τ and f max ≥ 200 GHz. A mesa DHBT process with and as much yield and simplicity as possible has been developed, while maintaining or pushing world-class performance.
Realization of high-speed to SHBTs using novel but simple techniques for parasitic reduction
16th IPRM. 2004 International Conference on Indium Phosphide and Related Materials, 2004., 2004
We have developed novel but simple process techniques for high speed InP SHBTs. For parasitic reduction, the collector layer is undercut using etch-stop layer, base pad is isolated, and emitter metal is widened using thick plated gold. Typical common emitter dc current gain (β) and BV CEO are about 25 and above 3.5 V, respectively at a collector current density of 1 × 10 5 A/cm 2 . Maximum extrapolated f max of 450 GHz with f T of 215 GHz is achieved for 0.5 × 8 µm 2 emitter area devices at I C = 17 mA and V CE = 1.5 V. These data clearly show that the optimized conventional process can offer the direct implementation of InP HBT for high-speed electronic circuit fabrication.
IEEE Journal of Solid-state Circuits, 2004
We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process we have demonstrated discrete SHBT with f t > 250 GHz and DHBT with f t > 230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicron emitters thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high performance HBTs and integrated circuits using a patterned implant on InP.
Current density limits in InP DHBTs: collector current spreading and effective electron velocity
16th IPRM. 2004 International Conference on Indium Phosphide and Related Materials, 2004., 2004
To minimize the dominant delay term in emitter-coupled logic, /spl Delta/V/sub logic/C/sub cb//I/sub c/, HBTs must operate at high current densities. Current density is limited by device thermal failure and by the Kirk effect. We here experimentally determine two key factors influencing the Kirk-effect limit. The collector current spreads laterally away from each side the emitter stripe over a distance /spl Delta/ approximately equal to the collector depletion thickness. This effect substantially increases the achievable current in submicron-emitter HBTs. Further, the variation of the Kirk-effect-limited current density with bias voltage indicates a 3.2(10/sup 5/) m/s effective collector electron velocity, consistent with that extracted from the measured transistor f/sub /spl tau//.
High-speed AlGaAs/GaAs HBTs with reduced base-collector capacitance
Electronics Letters, 2001
We present a new layout for high-speed AlGaAs/GaAs HBTs. The layout is horseshoe shaped and is designed to simultaneously reduce base resistance (R B) and base-collector capacitance (C BC). A horseshoe shaped HBT and a conventional singlefinger HBT with the same emitter width of 2 µm were fabricated and tested. The reduction of R B and C BC using the horseshoe shaped HBT resulted in 25 % improvement of maximum oscillation frequency (f max = 130 GHz).
InP DHBT-based IC technology for high-speed data communications
2005
In this paper, we report the achieved performance of devices and integrated circuits (ICs) using a manufacturable InP DHBT-based technology. High speed MBE grown InGaAs/InP DHBTs with an effective emitter junction area of 4.8 /spl mu/m/sup 2/ exhibited peak f/sub T/ and f/sub MAX/ values of 265 and 305 GHz, respectively, at a collector current density of 3.75 mA//spl mu/m/sup
SiGe HBTs With Normal High-Speed Emitter-Up and Reverse Low-Power Collector-Up Operation
IEEE Transactions on Electron Devices, 2008
SiGe heterojunction bipolar transistors (HBTs) are usually optimized to obtain best performance in the forward operation mode. In this paper, we demonstrate that a simultaneous excellent performance in the reverse mode of operation can be obtained as well. A f T /f max combination of 50/100 GHz is obtained, which is, to our knowledge, the best value reported for a Si-based HBT operating in the reverse mode. This excellent performance is analyzed and explained by studying the different delay components of the device in the reverse operation mode. It is shown that the extrinsic SiGe base region plays a crucial role. Additionally, good low-power performance in the reverse operation mode is obtained as well, which is attributed to a reduction in the device parasitic contributions. The simultaneous availability of a high-speed performance in the forward mode and a low-power performance in the reverse mode offers additional flexibility to optimize circuit performance in terms of speed, power, and area. Index Terms-Heterojunction bipolar transistor (HBT), silicon-germanium (SiGe). I. INTRODUCTION B IPOLAR transistors are normally operated in the forward active mode (emitter-up or collector-down configuration). The reverse active mode (emitter-down or collector-up configuration) is usually of less importance. This is because the performance of bipolar devices in the reverse active mode is inferior to that in the forward active mode as these devices are usually optimized to obtain the best forward characteristics. Using an emitter-down configuration has some advantages however [1]-[3]. First, in an emitter-down configuration, the base-collector area is minimal. Together with optimized doping profiles, these lead to small values for the base-collector capacitance, which is crucial for many circuits. Moreover, the collector resistance is strongly reduced. Second, as the collector is now on top of the device, the coupling with the substrate is reduced. Third, with the availability of emitter-down transistors, specific circuits can be laid out in a very compact form. Consider, for instance, making a current-mode logic (CML) or emitter-coupled logic gate using emitter-up transistors [Fig. 1(a) and (b)]. In this case, each transistor has to be isolated from each other, and the emitters of the switching pair are connected via the metal layer. However, when emitter-up
InP DHBT IC Technology with Implanted Collector Pedestal and Electroplated Device Contacts
2006 IEEE Compound Semiconductor Integrated Circuit Symposium, 2006
We report the development of a wide bandwidth InP double heterojunction bipolar transistor technology that incorporates an ion implanted N + collector-pedestal for reduction of extrinsic collector-base capacitance C cb . The technology also utilizes novel electroplating processes and dielectric sidewall spacers to eliminate traditional liftoff processes from the formation of a self-aligned base-emitter junction. Devices with 0.4 µm emitter junction widths demonstrate peak f τ and f max values of over 370 GHz. Importantly, the devices also demonstrate a significant reduction (~35%) in C cb versus HBTs with the same device footprint fabricated without a collector pedestal. Static frequency-divider circuits have been realized in the technology. A CML divide-by-two circuit demonstrated a maximum operating frequency of 128 GHz. This result demonstrated a ~20% improvement in operating frequency versus the same design realized in a non-collector-pedestal process.