Characterizing damage on Si wafer surfaces cut by slurry and diamond wire sawing (original) (raw)

Surface Damage Introduced by Diamond Wire Sawing of Si Wafers: Measuring in-depth and the Lateral Distributions for Different Cutting Parameters

MRS Proceedings, 2015

ABSTRACTThis paper describes the characteristics of damage, introduced under different conditions of diamond wire sawing, on the Si wafer surfaces. The damage occurs in the form of frozen-in dislocations, phase changes, and microcracks. The in-depth damage was determined by conventional ways such as TEM, SEM and angle-polishing/defect-etching, which only provide local information. We have also applied a new technique based on sequential measurement of the minority carrier lifetime after etching thin layers from the surfaces to determine average damage depth and its in-depth distribution. The lateral spatial damage variations, which seem to be mainly related to wire reciprocation process, were observed by photoluminescence and lifetime mapping. Our results show a strong correlation of damage depth on the diamond grit size and wire usage.

A method for determining average damage depth of sawn crystalline silicon wafers

Review of Scientific Instruments, 2016

The depth of surface damage (or simply, damage) in crystalline silicon wafers, caused by wire sawing of ingots, is determined by performing a series of minority carrier lifetime (MCLT) measurements. Samples are sequentially etched to remove thin layers from each surface and MCLT is measured after each etch step. The thickness-removed (δt) at which the lifetime reaches a peak value corresponds to the damage depth. This technique also allows the damage to be quantified in terms of effective surface recombination velocity (Seff). To accomplish this, the MCLT data are converted into an Seff vs δt plot, which represents a quantitative distribution of the degree of damage within the surface layer. We describe a wafer preparation procedure to attain reproducible etching and MCLT measurement results. We also describe important characteristics of an etchant used for controllably removing thin layers from the wafer surfaces. Some typical results showing changes in the MCLT vs δt plots for dif...

Surface characteristics and damage distributions of diamond wire sawn wafers for silicon solar cells

AIMS Materials Science, 2016

This paper describes surface characteristics, in terms of its morphology, roughness and near-surface damage of Si wafers cut by diamond wire sawing (DWS) of Si ingots under different cutting conditions. Diamond wire sawn Si wafers exhibit nearly-periodic surface features of different spatial wavelengths, which correspond to kinematics of various movements during wafering, such as ingot feed, wire reciprocation, and wire snap. The surface damage occurs in the form of frozen-in dislocations, phase changes, and microcracks. The in-depth damage was determined by conventional methods such as TEM, SEM and angle-polishing/defect-etching. However, because these methods only provide local information, we have also applied a new technique that determines average damage depth over a large area. This technique uses sequential measurement of the minority carrier lifetime after etching thin layers from the surfaces. The lateral spatial damage variations, which seem to be mainly related to wire reciprocation process, were observed by photoluminescence and minority carrier lifetime mapping. Our results show a strong correlation of damage depth on the diamond grit size and wire usage.

Surface damage in processed silicon

Materials Science and Engineering: B, 1996

The surface and sub-surface damage induced by processing is a major concern for the Si advanced sub-micron technologies. The interest in characterization techniques which allow monitoring of the modifications of the surface electrical properties of the Si wafers is, therefore, growing. The surface recombination velocity is the parameter more directly correlated to the recombination activity of the surface, and, therefore, more sensitive to the changes in the surface electronic properties, but its measurement, up to now, has not been assessed enough. We have measured the surface recombination velocity by two independent methods: the photoelectromagnetic effect (PEM) and the electron beam induced current (EBIC) mode of a scanning electron microscope (SEM), in order to test the reliability of the techniques and to correlate the macroscopic value obtained by PEM with the local values obtained by EBIC. In this work we report the results obtained on two types of processing damage: the surface modifications induced by rapid thermal annealing at 750 and 1050°C of n-type 10 52 cm silicon and the damage induced in the Si substrate by a SiCI, dry etching of a 5.500 w thick polysilicon film grown on n-type 1 fi cm CZ silicon. In both cases a very good agreement between the PEM and the EBIC values has been obtained. The correlation between the surface velocity recombination variations detected by EBIC and PEM and the data already obtained from the C-Y and I-V characteristics and lifetime measurements has been used to understand the type and the distribution of the process induced damage.

Surface damage and mechanical strength of silicon wafers

physica status solidi c, 2015

The fracture strength of silicon wafers used for photovoltaic and microelectronic applications mainly depends on the damage structure, which is introduced on the surface during processing of the wafers. The present paper investigates the formation and development of the damage structure by scratching, which occurs during grinding processes or when sawing with diamond coated wires. The basic scratching process has been studied with a newly developed scratch technique, where test parameters comparable to a real process could be used. Single scratch tests have been performed with diamond particles on monocrystalline silicon wafers with a defined surface orientation and under different applied forces. The resulting microcrack structure, which develops under the surface, has been investigated by confocal laser scanning microscopy, scanning electron microscope and Raman spectroscopy. Details of the shape, depth and distance of the cracks have been obtained by high quality sample cross sec...

Determination of the impact of the wire velocity on the surface damage of diamond wire sawn silicon wafers

Energy Procedia, 2015

The sawing of silicon wafers with diamond coated wires still requires further development for a widespread application in the photovoltaic industry. The technique has the potential for a cost reduction due to higher cutting rates and the use of water as a low-cost cooling fluid, but it is also necessary to integrate the technique into the established processing chains particularly for sawing multicrystalline silicon (mc-Si). One of the requirements is an increasing industrial demand on the wafer surface quality, such as the optical appearance, the total thickness variations (TTV), the etching behavior and the sub-surface and surface damage, which determines the mechanical wafer stability. The goal of this work is to analyze the impact of different wire velocities on the surface damage of multicrystalline silicon wafers. First, the distribution of amorphous regions was measured using Raman microscopy. The results reveal slightly higher local fractions of the amorphous phase with increasing wire velocity. This also correlates with more scattering and higher inhomogeneity in the surface roughness values. Furthermore, the microcrack depths were analyzed on polished and etched bevel cut samples of wafers using confocal laser scanning microscopy (CLSM). Additionally, the present study investigates the impact of cleaning procedures and different grain orientations on the sawing damage characteristics.

Analysis of the Sub-surface Damage of mc- and cz-Si Wafers Sawn with Diamond-plated Wire

Energy Procedia, 2013

The usage of diamond-plated wire to produce silicon wafers for the photovoltaic industry is still a new and highly investigated wafering technology. The requirements regarding the quality of the wafer surface are very high and they have to compete with the cost effectiveness and quality of wafers produced by the established loose abrasive sawing technology. Hence, the wafer topography, the fracture stress and the corresponding sub-surface damage have to be investigated and improved. This paper discusses the topographic parameters, the crack depths and the fracture stress of mono-and multicrystalline silicon wafers that were produced on multi-wire saws using diamond-plated wire and comparable process parameters. Especially multi-crystalline silicon (mc-Si) wafers exhibit lower fracture stress values compared to mono-crystalline silicon (cz-Si) wafers. We investigated the relations between crack depth and fracture stress. In detail, we determined a 15 % higher median and a 40 % increased interquartile range of the crack depth of mc-Si wafers in comparison to similar produced cz-Si wafers. That correlates with lower fracture stress values of textured mc-Si wafers compared to cz-Si wafers. In the following, we studied the sub-surface damage as a function of crystal orientation in detail. It was found that the crack depths increases from the {100} plane over the {111} plane to the {101} plane. However for the {101} plane two grains were investigated, resulting in a discrepancy of 4 μm. This may be related to the unknown rotation angle between the corresponding {111} cleavage planes and the wire direction and requires further investigations.

Damage Evaluation of Wet-Chemical Si-Wafer Thinning/Backside Via Exposure Process

IEEE Transactions on Components, Packaging and Manufacturing Technology

To realize low-cost and damage-less through silicon via (TSV) formation, we evaluated the damage caused by a new wet-chemical Si-wafer thinning/backside via exposure process. Damage at the etched Si subsurface was examined using ballon-ring tests, cross-sectional transmission electron microscopy, and electron energy loss spectroscopy. The die fracture load obtained after this process was higher than those for processes that include a backgrinding step. There was little damage to the etched Si subsurface layer after our new process. We then evaluated the damage in 0.8-µm metal-oxide-semiconductor fieldeffect transistor generated by the new process. The changes in threshold voltage, subthreshold swing, transconductance, and leakage current were very small, even when the wafer was thinned down to 20 µm. Finally, we applied our new process to a Cu/Ta via wafer to evaluate the damage in a TSV. No damaged layers were observed in the TSV, and the leakage current between the TSVs after this process was sufficiently small for practical application.

Study on the surface damage mechanism of monocrystalline silicon in micro ball-end milling

Precision Engineering, 2019

This paper investigates the surface damage mechanism of monocrystalline silicon in micro ball-end milling with polycrystalline diamond (PCD) and natural diamond tools. Machininginduced surface damages such as surface fracture, phase transition, and residual stress are studied under different machining conditions. It is found that under a small feed rate and cutting depth and high spindle speed, PCD micro ball-end mill is a potential candidate in manufacturing low-damage surfaces that are distributed uniformly with the amorphous layer of several-nanometer thickness and the average compressive residual stress that does not exceed 150 MPa. Additionally, the influences of feed rate on surface damages in PCD micro milling are more significant than those in micro milling with a natural diamond tool. The experimental results reveal the surface damage mechanism: (i) the current cutting region comprises the subsurface layer after machining in the last tooth period, the previously produced surface/subsurface defects can affect the damages of the current machined surface, (ii) the cutting edge closer to the tool tip acts primarily on amorphous silicon generated in the previous tooth period, part of the amorphous phase remains on the machined surface, and the formation of metastable phases (Si-III, Si-XII, and Si-IV