Speculative Execution and Timing Predictability in an Open Source RISC-V Core (original) (raw)
Related papers
MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution
IEEE Transactions on Computers
Predictable Programming on a precision timed architecture
Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08, 2008
Processor Support for Temporal Predictability - The SPEAR Design Example
PRET-C: A new language for programming precision timed architectures
… -Alpes, http://hal. inria. fr/inria …, 2009
The challenge of time-predictability in modern many-core architectures
2014
PRET-C: A New Language for Programming Precision Timed Architectures (extended abstract
Timing analysis of embedded software for speculative processors
15th International Symposium on System Synthesis, 2002., 2002
The Impact of Speculative Execution on SMT Processors
International Journal of Parallel Programming, 2007
Building timing predictable embedded systems
Heiko Falk, Alain Girault, Reinhard von Hanxleden, Rolf Ernst, Peter Marwedel
ACM Transactions on Embedded Computing Systems, 2014
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering, 1995
Blueshift: Designing processors for timing speculation from the ground up
2009
T.: Towards a time-predictable dual-issue microprocessor: The Patmos approach
2011
A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking
Exploring circuit timing-aware language and compilation
ACM SIGARCH Computer Architecture News, 2011
Predictable performance in SMT processors
2004
Identifying the sources of unpredictability in COTS-based multicore systems
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013
Forcing Some Architectural Ceilings of the Actual Processor Paradigm
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
Daniel Enrique Maldonado Sanchez
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach
Applied Reconfigurable Computing, 2017