Ge (100) and (111) N-and P-FETs With High Mobility and Low-Mobility Characterization (original) (raw)
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2008 IEEE International Electron Devices Meeting, 2008
High-k/Ge interfaces are significantly improved through a new interface engineering scheme of using both effective pre-gate surface GeO 2 passivation and post gate dielectric (post-gate) treatment incorporating fluorine (F) into high-k/Ge gate stack. Minimum density of interface states (D it) of 2 × 10 11 cm-2 eV-1 is obtained for Ge MOS capacitors. Hole mobility up to 396 cm 2 /Vs is achieved for Ge pMOSFETs with EOT ~10 Å and gate leakage current density less than 10-3 A/cm 2 at V t ± 1 V. Best drain current to date of 37.8 μA/μm at V g-V t = V d =-1.2V is presented for an L g of 10 µm. Variable rise and fall time charge pumping (CP) method is used to investigate Ge interface property and a significant D it reduction in both upper and lower half of bandgap is observed with F incorporation.
High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms
IEEE Transactions on Electron Devices, 2011
Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In this paper, mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analysis. High source/drain (S/D) parasitic resistance, inversion charge loss due to trapping in the high-K gate dielectric, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation. After eliminating the degradation mechanisms, the highest electron mobility in Ge NMOS to date, which is, to the best of our knowledge, ∼1.5 times the universal Si mobility, is experimentally demonstrated for the Ge N-MOSFETs fabricated with ozone-oxidation surface passivation and low temperature S/D activation processes.
The Effect of Donor/Acceptor Nature of Interface Traps on Ge MOSFET Characteristics
IEEE Transactions on Electron Devices, 2000
In this paper, the acceptor and donor nature of interface traps are investigated using conductance and interface trap time constant measurements on Ge n-and p-type metaloxide-semiconductor field-effect transistors (N-and PMOSFETs). The presence of acceptor-type interface trap states in the valence-band side of Ge band gap is confirmed by these measurements. Electron trapping by the acceptor-type interface states and their effect on Ge N-and PMOS performance are discussed. The high density of the acceptor-type interface traps found to be degrading Ge NMOSFET performance, while it is not a concern for Ge PMOSFETs because of the position of charge neutrality level in Ge. Trapped charge calculations show that reducing the interface trap density by the ozone oxidation mitigates the electron trapping by the acceptor-type traps, which otherwise degrade Ge NMOSFET performance. By engineering the gate dielectric interface of Ge NMOSFETs, 40% improvement in inversion electron mobility is reported. Improvement of 2.5× over universal hole mobility is achieved for Ge PMOSFETs.
Thin Solid Films, 2011
We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal-oxidesemiconductor field-effect transistor). The poor electron transport property is primarily attributed to the low dopant activation efficiency and high contact resistance. Results are supported by analyzing source/drain Ohmic metal contacts to n-type Ge using the transmission line method. Ni contacts to Ge nMOSFETs exhibit specific contact resistances of 10 − 3-10 − 5 Ω cm 2 , which is significantly higher than the 10 − 7-10 − 8 Ω cm 2 of Ni contacts to Ge pMOSFETs. The high resistance of Ni Ohmic contacts to n-type Ge is attributed mainly to insufficient dopant activation in Ge (or high sheet resistance) and a high tunneling barrier. Results obtained in this work identify one of the root causes of the lower than expected Ge nMOSFET transport issue, advancing high mobility Ge channel technology.
Interface-Engineered High-Mobility High- $k$ /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness
IEEE Transactions on Electron Devices, 2009
High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO 2 passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (D it) of 2 × 10 11 cm −2 • eV −1 for Ge MOS capacitors. A hole mobility up to 396 cm 2 /V • s is achieved for Ge p-metaloxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ∼10 Å and gate leakage current density that is less than 10 −3 A/cm 2 at V t ± 1 V. A high drain current of 37.8 μA/μm at V g − V t = V d = −1.2 V is presented for a channel length of 10 μm. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times D it reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.
ECS Solid State Letters, 2014
We demonstrate thin body GeOI Pseudo-MOSFETs fabricated by a novel GeOI fabrication process based on epitaxial Ge films grown on III-V compound semiconductor wafers and wafer bonding. Ge surfaces before bonding are treated by plasma post oxidation to form GeO x , which can provide better interfacial quality between Ge and buried oxides. Normal operations of n-and p-MOSFETs are confirmed for GeOI with average thickness of 60 to 20 nm. The peak effective hole and electron mobility of 122 and 235 cm 2 /Vs, respectively, have been obtained for 20-nm-thick-GeOI n-and p-MOSFETs. The GeOI thickness dependence of mobility is also examined.
We investigated magnetoresistance of p-type Ge-on-Si metal-oxide-semiconductor field-effect transistors in order to determine the hole mobility µ as a function of the gate polarization (VG). Measurements were carried out at 4.2 K and magnetic fields up to 10 T. The signal measured was proportional to the derivative of the transistor resistance with respect to VG. To determine the hole mobility we developed a method to treat the measured signal which is based on a numerical solution of a differential equation resulting from the theoretical description of the experimental procedure. As a result, we obtained a non-monotonic µ(VG) dependence which is a characteristic feature of the carrier transport in gated two-dimensional structures.
Journal of The Electrochemical Society, 2008
Germanium possesses higher electron and hole mobilities than silicon. There is a big leap, however, between these basic material parameters and implementation for high-performance microelectronics. Here we discuss some of the major issues for Ge metal oxide semiconductor field effect transistors ͑MOSFETs͒. Substrate options are overviewed. A dislocation reduction anneal Ͼ800°C decreases threading dislocation densities for Ge-on-Si wafers 10-fold to 10 7 cm −2 ; however, only a 2 times reduction in junction leakage is observed and no benefit is seen in on-state current. Ge wet etch rates are reported in a variety of acidic, basic, oxidizing, and organic solutions, and modifications of the RCA clean suitable for Ge are discussed. Thin, strained epi-Si is examined as a passivation of the Ge/gate dielectric interface, with an optimized thickness found at ϳ6 monolayers. Dopant species are overviewed. P and As halos are compared, with better short channel control observed for As. Area leakage currents are presented for pϩ/n diodes, with the n-doping level varied over the range relevant for pMOS. Germanide options are discussed, with NiGe showing the most promise. A defect mode for NiGe is reported, along with a fix involving two anneal steps. Finally, the benefit of an end-of-process H 2 anneal for device performance is shown.
Journal of Applied Physics, 2004
Strained Si ͑-Si͒ grown on Si-rich relaxed Si 1Ϫx Ge x buffers ͑single-channel heterostructures͒ can be used to fabricate n-channel metal-oxide-semiconductor field-effect transistors ͑n-MOSFETs͒ with enhanced performance over bulk Si. However, single-channel heterostructures grown on Ge-rich Si 1Ϫx Ge x buffers ͑i.e., xу0.5) exhibit much larger hole mobility enhancements than those on Si-rich buffers, and the highest hole mobilities have been attained in heterostructures where a compressively strained Ge ͑-Ge͒ layer is grown beneath the-Si cap ͑-Si/-Ge dual-channel heterostructures͒. In this article, we report on n-MOSFET mobility characteristics in single-and dual-channel heterostructures grown on Ge-rich Si 1Ϫx Ge x buffers. Single-channel n-MOSFETs were fabricated on virtual substrates with Ge contents as high as 70%, and electron mobility enhancements of 1.4-1.6 were observed. For dual-channel heterostructures, electron mobility enhancements of 1.7-1.9 were attained when the-Si cap was thick enough to confine electrons. Despite the high intrinsic electron mobility of bulk Ge, dual-channel n-MOSFETs with extremely thin Si caps ͑ϳ3 nm͒ exhibited mobility significantly below that of bulk Si. We speculate that the low extracted mobility in such heterostructures results from the difference in conduction band minima between Ge and Si.
Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs
ESSDERC 2008 - 38th European Solid-State Device Research Conference, 2008
The semiconductor-dielectric interface passivation of Ge pMOSFETs with an epitaxially grown Si-layer is studied by means of the full conductance technique. This technique resolves several issues which occur for alternative MOSinterfaces when using the 'classical' conductance technique. The observed mobility behavior as a function of Si-passivation thickness can be explained by the observed variation in interface state density. Observed threshold voltage shifts as a function of Si-passivation thickness can also be linked to the variation in interface state density with thickness.