Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging (original) (raw)
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The growing interest in improving optoelectronic devices requires continuous research of the materials and processes involved in manufacturing. From a chemical point of view, the study of this sector is crucial to optimize existing manufacturing processes or create new ones. This work focusses on the experimental evaluation of residual stresses on samples that are intended to simulate part of the structure of an optoelectronic device. It represents an important starting point for the development of optoelectronic devices with characteristics suitable for future industrial production. Silicon chips, with a thickness of 120 μm, were soldered onto copper and alumina substrates, using different assembly parameters in terms of temperature and pressure. Using Raman spectroscopy, the stress evaluation was estimated in a wide temperature range, from −50 to 180 °C. Silicon chips soldered with AuSn alloy on copper substrates demonstrated at 22 °C a compressive stress, developed in the center ...
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Deep boron diffused pþþ silicon layer is a powerful tool in determining the thickness of bulk micromachined MEMS structures. However, due to the large incorporation of boron atoms, high levels of residual stress are generated in these structures. But, there is very little report on the estimation of residual stress in deep boron diffused pþþ silicon layer. This paper presents the optimization of deep boron diffusion (boron concentration 4 5 Â 10 19 atoms/cm 3 having thickness 410 mm) in silicon (100), (110) and (111) wafers. The silicon samples are characterized (before and after the diffusion process) using Raman spectroscopy and scanning electron microscopy (SEM). From this study, the residual stress generated for the Si(100), (110) and (111) samples are 454.61 MPa, 908.58 MPa and 908.67 MPa respectively. Disparities in residual stress values in the silicon wafers are also correlated.
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