Characterization of microprocessor chip stress distributions during component packaging and thermal cycling (original) (raw)

Measurement of die stress distributions in flip chip CBGA packaging

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2010

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as the stress changes occurring due to thermal cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers.

Stress measurements in large area array flip chip microprocessor chips

2008 58th Electronic Components and Technology Conference, 2008

Application of stress sensing test chips to area array packaging

EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, 2009

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling.

Characterization of Stress in High Performance Server Microprocessors

Continuous In-Situ Die Stress Measurements During Thermal Cycling Accelerated Life Testing

2007 Proceedings 57th Electronic Components and Technology Conference, 2007

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling.

Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping

ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1, 2011

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/ speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete threedimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general "rule of thumb," approximately two-thirds ($66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to À 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

Die stress characterization in flip chip on laminate assemblies

IEEE Transactions on Components and Packaging Technologies, 2000

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from 40 to +150 C.

Die stress variation in area array components subjected to accelerated life testing

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 2008

Thermal cycling accelerated life testing is often used to qualify packages for various applications. Finite element life predictions for thermal cycling configurations is challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling.

Determination of Thermal Induced Stresses in Semiconductor Chip Package by using Finite Element Analysis: A Brief Review

International Journal of Engineering Research and, 2015

In todays advanced electrical technology, it becomes necessity to use compact semiconductor chips in variety of areas like computers, electrical appliances, automotive etc., clearly the need of more and more sophisticated packages is increasing. As the need of faster computer increases design of denser and more complicated packages becomes unavoidable, more complicated packages means that, the size of chip more or less remains same, but it has more electronic circuitry per unit surface area, this, of course increases the temperature of packages and causes thermal expansion due to change in coefficient of thermal expansion of the constituent materials. Thermal stresses ultimately cause the failure of the device. An IC package mainly consist of four parts, silicon die (chip), polymeric substrate, plastic molding compound and connectivity parts, lead frames and bond wires. The silicon chip is assembled on a polymeric substrate, plastic molding compound surrounding both parts, lead frames and bond wires provide electrical connectivity between the package and board on which assembly is made. The complicated geometrical structure and different material properties as well as the loading conditions made it almost impossible to study the mechanical behavior of semiconductor package analytically; therefore the finite element method has become a useful tool for evaluation of problems encountered in this area.

Evaluation of Die Stress in MEMS Packaging: Experimental and Theoretical Approaches

IEEE Transactions on Components and Packaging Technologies, 2006

The device performance of microelectromechanical system (MEMS) inertial sensors such as accelerometers and gyroscopes is strongly influenced by the stress developed in the silicon die during packaging processes. This is due to the die warpage in the presence of the stress. It has previously been shown that most of the stress is generated during a die-attach process. In this study, we employ both experimental and theoretical approaches to gain a better understanding in a stress development induced during the packaging processes of a small silicon die (3.5 3.5 mm 2). The former approach is accompanied with an optical profilometer while the latter part by a finite element analysis and an analytical model. A specific emphasis is given to the effects of structural parameters such as the die-attach adhesive thickness and material properties on the stress development. The results from all three approaches show good agreement, in that more compliant and thicker adhesives offer great relief in the stress development, as well as bend the die convex downward from its central location. A stress model proposed from this study not only provides a diagnostic tool for very small stress-sensitive devices, but it will also present a design tool for low-stress MEMS packaging systems.

Characterization of microprocessor chip stress distributions during component packaging and thermal cycling (original) (raw)

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