In-Place Delay Constrained Power Optimization Using (original) (raw)
Related papers
In-place delay constrained power optimization using functional symmetries
Design, Automation, and Test in Europe, 2001
In-Place Optimization (IPO) has become the backend methodology of choice to resolve the gap between logic synthesis and physical design as the optimization can be guided by accurate physical information. To perform optimization without perturbing too much the placed netlist, only buffer insertion and gate sizing are commonly used in current design tools. In this paper, we address the problem of delay-constrained power optimization by introducing another degree of freedom: functional symmetry based rewiring. Theoretical results on the effect of using functional symmetry on transition density for power estimation is also derived. Experimental results show that, under the same delay constraint, our technique achieves much better power reduction as compared to the discrete gate sizing only technique.
1993
In this paper we address the problem of optimization of VLSI circuits to minimize power consumptioin while meeting performance goals. We present a method of estimating power consumptioin of a basic or complex CMOS gate which takes the internal cap,acitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library based design styles. We describe a multi-pass algorithm which makes use of transisto1 reordering to optimize performance and power consumption of circuits, which has a linear time complexity per pass and which converges to a solution in ,X small number of passes. Transformations besides transistor reordering can be used by the algorithm. The algorithm h i~s been benchmarked on several large examples and the results are presented.
Transistor reordering for power minimization under delay constraint
ACM Transactions on Design Automation of Electronic Systems, 1996
In this article we address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. The method is very efficient when used by library-based design styles. We describe a multipass algorithm that makes use of transistor reordering to optimize performance and power consumption of circuits, has a linear time complexity per pass, and converges to a solution in a small number of passes. Transformations in addition to transistor reordering can be used by the algorithm. The algorithm has been benchmarked on several large examples and the results are presented.
Data driven power optimization of sequential circuits
Proceedings Design, Automation and Test in Europe, 2000
In this paper we present an e cient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates (targets) such that the switching activities at the output of the targets are signi cantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement 11, 12]. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of the proposed transformation is polynomial in the size of the circuit, allowing the processing of large designs.
Enhancing sensitivity-based power reduction for an industry IC design context
Integration, 2019
For many years, discrete gate sizing has been widely used for timing and power optimization in VLSI designs. The importance of gate sizing optimization has been emphasized by academia for many years, especially since the 2012/2013 ISPD gate sizing contests [1, 2]. These contests have provided practical impetus to academic sizers through the use of realistic constraints and benchmark formats. At the same time, due to simplified delay/power Liberty models and timing constraints, the contests fail to address real-world criteria for gate sizing that are highly challenging in practice. We observe that lack of consideration of practical issues such as electrical and multi-corner constraints-along with limited sets of benchmarks-can misguide the development of contestfocused academic sizers. Thus, we study implications of the "gap" between academic sizers and product design use cases. In this paper, we note important constraints of modern industrial designs that are generally not comprehended by academic sizers. We also point out that various optimization techniques used in academic sizers can fail to offer benefits in product design contexts due to differences in the underlying optimization formulation and constraints. To address this gap, we develop a new robust academic sizer, Sizer, from a fresh implementation of Trident [3]. Experimental results show that Sizer is able to achieve up to 10% leakage power and 4% total power reductions compared to leading commercial tools on designs implemented with foundry technologies, and 7% leakage power reduction on a modern industrial design in the multi-corner multi-mode (MCMM) context.
Driven Logic Synthesis for Area and Power Minimization
2007
In this paper we present the application of our ATPGbased design rewiring approach to multi-level combinational logic circuit optimization. At every step of this optimization procedure, we introduce a design error by removing the logic that violates the optimization constraint(s) and then we attempt to correct the design by modifying the logic somewhere else. We give heuristics and describe the application of this method to delay optimization and to design for low power. Experiments are also presented to support the potential of our method. Ivor Ting Andreas Veneris Magdy S. Abadir Alcatel University of Toronto Motorola 4190 Still Creek Drive Dept ECE and CS 7700 W. Parmer Burnaby, BC V5C 6C6 Toronto, ON M5S 3G4 Austin, TX 78729 ivor.ting@alcatel.com veneris@eecg.toronto.edu m.abadir@motorola.com
2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008
Minimizing power consumption is one of the most important objectives in VLSI design. This paper introduces a methodology for the optimization of total power consumption of template based asynchronous circuits via dual V dd assignment, dual V th assignment and template sizing while maintaining performance requirements. The utilized circuit model is a Timed Petri-Net which captures the dynamic behavior of the circuit. These three power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 65 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty. From the experimental results, we show that the combination of asynchronous design and three low power techniques is an effective way to achieve low power and high performance circuits.
Evaluating the Effectiveness of Statistical Gate Sizing for Power Optimization
2000
We evaluate the eectiv eness of statistical gate sizing to min- imize circuit power. We develop reliable posynomial models for delay and power that are accurate to within 5-10% of 130nm library data. We formulate statistical sizing as a ge- ometric program, accounting for randomness in gate delays. For various ISCAS-85 circuits, statistical sizing at a 99.8% target yield provides
With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters I gratefully acknowledge the support of IDA Ireland and Synopsys for the financial support of this work. Lastly to my fianc Vivek who has always been a tremendous source of encouragement, confidence and love. v
Gate Sizing Minimizing Delay and Power/Area
In this work we present a gate sizing tool based on Geometric Programming. The optimization can be done targeting both, delay and power/area minimization. In order to qualify our approach, the ISCAS'85 benchmark circuits are mapped for 350nm and 45nm technologies using typical standard cell libraries. Next, the mapped circuit is sized using our tool and the result is comparated to the original mapped circuit. The speed is increased by 21% and 4.5%, on average, for 45nm and 350nm technology, respectively, keeping the same area and power values of the sizing provided by standard-cells library. For power/area optimization, where the delay was restricted to the delay value found at delay minimization, the reduction was 28.2% in area and 27.3% in power consumption, on average, considering 45nm technology and 29.9% in area and 28.5% in power, on average, considering 350nm technology.