50 nm Vertical Replacement-Gate (VRG) pMOSFETs (original) (raw)

The vertical replacement-gate (VRG) MOSFET

D. Monroe

Solid-State Electronics, 2002

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The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length

Frieder Baumann

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999

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MBE-grown vertical power-MOSFETs with 100-nm channel length

Jörg Schulze

Thin Solid Films, 2000

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Vertical MOSFETs for High Performance, Low Cost CMOS

Octavian Buiu

2007 International Semiconductor Conference, 2007

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25-nm p-channel vertical MOSFETs with SiGeC source-drains

Malcolm Carroll

IEEE Electron Device Letters, 2000

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Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth

M. Marso

Solid-State Electronics, 1999

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50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics

D. Monroe

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001

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Sub-50 nm P-Channel FinFET

疵屋 吳

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CHALLENGES AND PROGRESS IN III-V MOSFETs FOR CMOS CIRCUITS

wilman tsai

International Journal of High Speed Electronics and Systems, 2008

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Improved vertical MOSFET performance using an epitaxial channel and a stacked silicon-insulator structure

Octavian Buiu

Semiconductor Science and Technology, 2012

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Thorough characterization of deep-submicron surface and buried channel pMOSFETs

Jalal Jomaah

Solid-state Electronics, 2002

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Gate engineering for deep-submicron CMOS transistors

Tsu-Jae Liu

1998

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Vertical integrated-gate CMOS for ultra-dense IC

Albert Chu

Microelectronic Engineering, 2006

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A novel 50 nm vertical MOSFET with a dielectric pocket

Sagnik Dey

Solid-state Electronics, 2006

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High-Performance Deep Submicron Ge pMOSFETs With Halo Implants

Brice de Jaeger

IEEE Transactions on Electron Devices, 2000

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Recent developments in deca-nanometer vertical MOSFETs

Octavian Buiu

Microelectronic Engineering, 2004

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Ge deep sub-micron HiK/MG pFETs with superior drive compared to Si HiK/MG state-of-the-art reference

V. Terzieva, Matthias Bauer, Frederik E . Leys

Semiconductor Science and Technology, 2007

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Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs

W. Rausch

IEEE Transactions on Electron Devices, 2000

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High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: VrmthV_{\rm th}Vrmth Tuning, Variability, Access Resistance, and Mobility Issues

A VILLALON

IEEE Transactions on Electron Devices, 2013

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Vertical 100 nm Si-p channel JFET grown by selective epitaxy

R. Loo

Applied Surface Science, 1996

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Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length = 13 nm) Considering Supply Voltage

gaya thri

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Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

Anish Dangol

Japanese Journal of Applied Physics, 2014

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Design and optimization of vertical surrounding gate MOSFETs for enhanced transconductance-to-current ratio ( g m/ I ds)

Rahul Gupta

Solid-state Electronics, 2003

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Multigate silicon MOSFETs for 45nm node and beyond

J. Widiez, T. Poiroux

Solid-State Electronics, 2006

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Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

Guido Groeseneken

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012

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Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

Octavian Buiu

IEEE Electron Device Letters, 2006

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Design and Simulation Analysis of Vertical Double-Gate MOSFET (VDGM) Structure for Nano-Device Application

Bablu Ghosh

International journal of simulation: systems, science & technology

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Extending planar single-gate CMOS & accelerating the realization of double-gate/multi-gate CMOS devices

John Borland

ULSI process integration …, 2003

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