Gate oxide reliability projection to the sub-2 nm regime (original) (raw)
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Ultra-thin gate oxide reliability projections
Solid-State Electronics, 2002
We describe the reliability projection methods currently used and show that 1.6 nm oxides are sufficiently reliable even if soft breakdown is considered the point of failure. We also explore the possibility of using oxides after soft breakdown. Ó
Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation
IEEE Transactions on Device and Materials Reliability, 2007
Gate-oxide breakdown is a key mechanism limiting IC lifetime. Lifetime is typically extrapolated from accelerated tests on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This paper details a capacitor-based model and compares the predictions of the model to results from accelerated lifetest of actual logic CPU products, discussing the assumptions which make such a comparison necessary. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that important factors included the different sensitivities of logic circuits versus cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data, including these effects. Once a model is validated, this paper discusses how it can be used to assess the reliability impact of changes in silicon processing and product use conditions.
Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability
Microelectronics Reliability, 2007
Gate oxide breakdown has been historically considered a catastrophic failure mechanism for CMOS technology. With CMOS downscaling the mid 1990's have seen the emergence of soft breakdown as a possible failure mode. At the same time the notion started appearing that the first breakdown event does not necessarily spell the immediate failure of the entire CMOS application. Relaxation of the CMOS circuit reliability criteria, however, requires a thorough understanding of the impact of the breakdown path on FET behavior. This cannot be consistently achieved without the microscopic perspective of the physical effects occurring in the affected device. Future CMOS applications will be able to sustain many soft breakdown events, which will be treated as additional parametric variation. Tools ranging from simulation to circuit monitoring will assure reliability at the functional level.
Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown
2006
Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown is typically characterized on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This work compares the predictions of capacitor-based models to results from accelerated lifetest of logic CPU products. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that an important factor was the different sensitivities of logic circuits vs. cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data including these effects. Once a model is validated, the paper discusses how it can be used to assess the reliability impact of changes in processing, use conditions, and circuit design.
A statistical approach for full-chip gate-oxide reliability analysis
International Conference on Computer Aided Design, 2008
Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxide thickness varies from die-to-die and within-die and as the precision of process control worsens an alternative reliability analysis approach is needed. In this work,
The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits
Solid-State Electronics, 2016
As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability-related variability) is an emerging concern that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects. The properties of gate oxide defects are discussed. It is further shown how in particular the electrical properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.
Dielectric breakdown mechanisms in gate oxides
Journal of Applied Physics, 2005
In this paper we review the subject of oxide breakdown ͑BD͒, focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1 nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during which the gate leakage increases above acceptable levels. In conditions of intrinsic BD, the leakage increase is due to the growth of damage within the oxide in localized regions. Observations concerning this damage are reviewed and discussed. The measurement of the current, voltage, and power dissipated during the BD transient are also reported and discussed in comparison with the data of structural damage. We then describe the current understanding concerning the dependence of the BD current transient on the conditions of electric field and voltage. In particular, as the oxide thickness and, as a consequence, the voltage levels used for accelerated reliability tests have decreased, the BD transient exhibits a marked change in behavior. As the stress voltage is decreased below a threshold value, the BD transient becomes slower. This recently discovered phenomenon has been termed progressive BD, i.e., a gradual growth of the BD spot and of the gate leakage, with a time scale that under operation conditions can be a large fraction of the total time to BD. We review the literature on this phenomenon, describing the current understanding concerning the dependence of the effect on voltage, temperature, oxide thickness, sample geometry, and its physical structure. We also discuss the possible relation to the so-called soft oxide BD mode and propose a simpler, more consistent terminology to describe different BD regimes. The last part of the paper is dedicated to exploratory studies, still at the early stages given the very recent subject, concerning the impact on the BD of materials for the metal-oxide-semiconductor gate stack and, in particular, metal gates.
Prediction and Modeling of Thin Gate Oxide Breakdown Subject to Arbitrary Transient Stresses
IEEE Transactions on Electron Devices, 2010
A reliable dielectric breakdown model under transient stresses via an extension of the power law is demonstrated. The model, which is based on the percolation model and the assumption of no significant detrapping, is successfully used in ramped voltage stress breakdown analysis. A demonstration of the model's validity consists of applying repetitive time-variant voltage waveforms-pulses, sine waves, ramps, and noise-until breakdown and, consequently, comparing prediction to reality. The breakdown distribution is initially derived from DC measurements, with the model predicting both the center and the shape of the distribution. Index Terms-Charged device model (CDM), gate oxide breakdown (GOB), power law (PL), time-dependent dielectric breakdown (TDDB), very fast transmission line pulse (VFTLP).
IEEE Transactions on Electron Devices, 2004
This paper deals with the statistics of successive oxide breakdown (BD) events in MOS devices. Correlation effects between these successive events are experimentally related to the statistics of BD current jumps, thus suggesting that they are related to lateral propagation of the BD path. The application of the successive BD theory to chip reliability assessment is discussed. Several failure criteria and the related reliability methodologies are considered and some of their limits are established.
2005
A theory of the Current-Ratio technique, which is widely used to locate gate oxide breakdown spots in one dimension (i.e., distance from source or drain), is proposed and verified. The theory shows that the Current-Ratio method is a special case of generalized van der Pauw technique, and as such, can easily be generalized to locate oxide breakdown spots in two dimensions. We develop the theoretical framework of this new class of breakdown-spot characterization techniques and then validate the theory by experiments. We conclude by discussing the implications of locating breakdown spots in two dimensions for reliability projections of ultra-thin gate oxides.