Compiler-optimized usage of partitioned memories (original) (raw)

Compilation techniques for energy reduction in horizontally partitioned cache architectures

Aviral Shrivastava

2005

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Energy-aware Allocation of Dynamic Variables in Partitioned Memory Architectures

Renato Levy

2000

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A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures

Aviral Shrivastava

2008

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Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

Constantine Polychronopoulos

Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998

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Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures

Aviral Shrivastava

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000

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Static Program Partitioning for Embedded Processors

Uday Khedker

Citeseer

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Power efficient instruction caches for embedded systems

Walid Najjar

2005

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EFFICIENT CACHE PARTITIONING TECHNIQUE FOR CHIP MULTIPROCESSORS

Research Papers

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A recursive algorithm for low-power memory partitioning

M. Poncino

Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00, 2000

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Heterogeneous memory management for embedded systems

Dave Stewart

Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01, 2001

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Improving the energy behavior of block buffering using compiler optimizations

Ugur Sezer

ACM Transactions on Design Automation of Electronic Systems, 2006

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A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Sarah Bird

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

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Architectural and compiler techniques for energy reduction in high-performance microprocessors

Constantine Polychronopoulos

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000

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A Compiler-Based Approach for Dynamically Managing Scratch-Pad Memories in Embedded Systems

J. Ramanujam

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004

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Discovering Cache Partitioning Optimizations for the K Computer

Swann Perarnau

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Fast, predictable and low energy memory references through architecture-aware compilation

Manish Verma

2004

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High Performance Embedded Architectures and Compilers

Per Stenstròˆm

Lecture Notes in Computer Science, 2005

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Throughput optimization via cache partitioning for embedded multiprocessors

J. van Eijndhoven

2006

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Application-specific memory management for embedded systems using software-controlled caches

Larry Rudolph

Proceedings of the 37th conference on Design automation - DAC '00, 2000

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Design space optimization of embedded memory systems via data remapping

Pinar Korkmaz

Sigplan Notices, 2002

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Compiler Support for Scalable and Efficient Memory Systems,

Rajeev Barua

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Automatic memory partitioning and scheduling for throughput and power optimization

Yi Zou

ACM Transactions on Design Automation of Electronic Systems, 2011

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Use of shared memory in the context of embedded multi-core processors: exploration of the technology and its limits

Paolo Burgio

2013

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Static resource models for code-size efficient embedded processors

Twan Basten

ACM Transactions on Embedded Computing Systems, 2003

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Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems

Abu Asaduzzaman

Microprocessors and Microsystems, 2009

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Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

Claude Ghez

International Symposium on System Synthesis (IEEE Cat. No.01EX526)

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