Domino logic with variable threshold voltage keeper (original) (raw)

A LITERATURE SURVEY AND INVESTIGATION OF VARIOUS HIGH PERFORMANCE DOMINO LOGIC CIRCUITS

In deep sub-micron regions, the dynamic power and abstaining reliability problems will be reduced when the power supply voltage was trimmed down. The consumption of power in highly performing circuits has climbed to the level where it enforces the most important limitation to the rising performance and functionality. If power consumption is keep on increasing then the highly performing circuits will start to intake power in terms of more than thousands. The foremost factor in CMOS technology based design is dynamic switching power which can be reduced by reducing the supply voltage. If the supply voltage is reduced then it automatically reduced the transistor current which affects the speed of the circuit. The threshold voltages are scaled down so that it will compensate the speed of the circuit which was affected because of lowering the supply voltage. It also helps to maintain the dynamic power consumption with sufficient level without affecting the performance of the circuit. As a result of threshold voltage reduction the sub threshold leakage current starts increasing exponentially. It will be a tremendous boost in the designing of energy efficient circuits which was focusing on lowering the leakage current. The domino logic circuit design techniques are suitable for highly performing circuits for its higher speed and uniqueness of area in comparison with Static CMOS Circuits. The noise margin illustrates significant reduction if the domino logic circuits were operated in deep sub micrometer. In this paper, a literature survey and investigation of various domino logic circuits have been carried out stating their features, advantages and disadvantages in a profound manner.

Domino logic with an efficient variable threshold voltage keeper

IEEE International Symposium on Circuits and Systems, 2005

In this work, domino logic with a variable threshold voltage keeper which uses an efficient body bias is proposed. The generator which consists of a capacitor and a diode is based on the voltage doubler technique. In the proposed scheme, the keeper size may be increased to improve the noise-immunity of the domino logic without significantly increasing the power and

A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors

International Journal of Computer Applications, 2013

Among the assorted logic styles used in fostering the integrated circuits, the domino logic styles offers higher speed and smaller transistor count as compared to the static cmos circuits. However the domino logic suffers from lower noise immunity and higher power dissipation due to the problem of charge sharing and sub-threshold leakage currents. In this paper some of the earlier proposed techniques to reduce the power consumption of the domino circuits like Dual threshold voltage (DTV) and Dual threshold voltage-voltage scaling(DTVS) have been analyzed. A novel stacked transistors Dual threshold voltage (ST-DTV) approach which deploys DTV technique with stacked transistors together with a voltage regulated static keeper is analyzed to abate the total power dissipation of the circuit together with a better Power delay product (PDP). The ST-DTV design is tested on a 3input OR gate and a 4x1 multiplexer at 90nm technology on multiple voltages and frequencies. Tanner tool EDA v13.0 is used for simulation.

A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting. This paper also analyses the PDP of the circuit at very low voltage and different W/L ratio of the transistors.

A low-power circuit technique for domino CMOS logic

Dynamic logic style is used in high performance circuit designs because of its faster speed and lesser transistor requirement as compared to static CMOS logic style. Dynamic logic has inherent disadvantages like less noise immunity and high power consumption. In this paper we have proposed a novel circuit technique for implementing dynamic gate. The proposed circuit has very less power dissipation with almost same noise immunity compared to the recently proposed circuit techniques for dynamic logic styles to improve noise immunity. The concept is validated through extensive simulation.

Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

2014

The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported...

Speed and Noise Immunity Enhanced Low Power Dynamic Circuits

Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a standard domino circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.

Domino Logic Topologies of OR Gate with Variable Threshold Voltage Keeper

In this paper, we tend to take four domino circuit topologies to boost the strength and lower the consumption of power. A high speed and noise immune domino logic circuit is given that uses the property of the footer semiconductor to raise the sensitivity of the dynamic node to noise and eventually in improved performance. Dynamic logic circuits are used for prime performance and high speed applications. We tend to analyze and compare completely different domino logic style topologies for lowering the sub-threshold outpouring current in standby mode NMOS block , increasing the speed and increasing the noise immunity. We tend to compare power, delay, and Power Delay Product (PDP) of various topologies. Simulation is finished employing a 45nm cadence tool for eight input OR circuit. Our projected circuits scale back power consumption by 100 percent to 35 the troubles, improvement of unity noise gain of 39% to 85% and have a higher figure of advantage as compared to conditional keeper domino. The simulation results unconcealed that prime Speed Conditional keeper Domino (CKD) circuit offers the most effective ends up in terms of reduction in delay and power consumption as compared to different circuits.

Compensating for the keeper current of CMOS domino logic using a well designed NMOS transistor

Domino CMOS logic finds a wide variety of applications due to their high speed and low device count. However, this type of logic has the drawback of low noise immunity especially when compared to complementary CMOS logic. This is due to the leakage current and charge sharing. So, a PMOS keeper must be used in order to compensate for this leakage. However, the use of a keeper in the conventional domino circuit degrades the speed of the circuit or results in an erroneous output due to the contention current. In this paper, a novel technique that acts to speed up the operation of domino logic and to improve its noise immunity using a weak keeper is proposed. In this technique, a well designed NMOS transistor will be connected to the dynamic node in order to draw the contention current during the evaluation phase. The term "well designed" will be illustrated through the paper. A modification to the proposed technique will also be presented in which the precharge device need not be increased in size. Simulation will be carried out for the 0.13 µm technology with V DD =1.2 V for the case of AND gate with two inputs. Simulation results show that the speed improves by a factor of approximately 33% and the noise margin increases from only 100 mV to 600 mV in case the dynamic node is to be at logic "0" for the same transistor aspect ratios at the cost of adding only one NMOS transistor and increasing the size of the precharge device, or instead connecting two serially connected NMOS transistors to the dynamic node and keeping the size of the precharge device the same.