(Ba,Sr)TiO3 dielectrics for future stacked- capacitor DRAM (original) (raw)
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Microstructure and Nonstoichiometry of Barium Strontium Titanate thin films for dram Applications
MRS Proceedings, 1999
In this paper we investigate the microstructural accommodation of nonstoichiometry in (BaxSr1-x)Ti1+yO3+Z thin films grown by chemical vapor deposition. Films with three different (Ba+Sr)/Ti ratios of 49/51 (y=0.04 in the notation of the formula above), of 48/52 (y = 0.08) and of 46.5/53.5 (y=0.15), were studied. High-resolution electron microscopy is used to study the microstructure of the BST films. High-spatial resolution electron energy-loss spectroscopy (EELS) is used to reveal changes in chemistry and local atomic environment both at grain boundaries and within grains as a function of titanium excess. We find an amorphous phase at the grain boundaries and grain boundary segregation of excess titanium in the samples with y=0.15. In addition, EELS is also used to show that excess titanium is being partially accommodated in the grain interior. Implications for the film electrical and dielectric properties are outlined.
Microelectronic Engineering, 2011
In this work, we have prepared metal-insulator-metal capacitors for dynamic random access memory capacitor application using atomic layer deposition of TiO 2 high-j dielectric and RuO 2 bottom electrode. We compare TiO 2 layers grown using TiCl 4 precursor or Ti-tetra-isopropoxide precursor, and Al-doped TiO 2 layers grown using Ti-tetra-isopropoxide precursor. The capacitors were analyzed in the terms of capacitance -voltage and current -voltage measurements and transmission electron microscopy imaging.
Journal of Applied Physics, 1995
Thin film non-volatile memory devices are fabricated on glass substrates by evaporating KNO 3 in an ultra high vacuum system. The top and bottom gold electrodes [25 lam x 25 ~tm] are deposited by shadow masking in the same vacuum system. The KNO 3 is protected from moisture by depositing a passivation layer of SiO. Pulse switching characteristics of thes~thin film memory devices show excellent signal-to-noise ratios for nonlinear and linear behavior. The integration of these transient current vs. time curves yields large values of spontaneous polarization (Ps,~ 10 3 t.tC cm 2). Capacitance-voltage measurements made at high frequency (1 MHz) with slow ramp rates (200mVs-l-2Vs-1) indicated well-defined threshold voltages and the presence of mobile carriers.
2019
Ba1-x(Sr)xTiO3 (x=0.3mol) (BST) powder was formulated and prepared by solid state mixed oxide route. The phase evaluation and structural properties of BST powder were studied by X-ray Diffractometer (XRD) with the Bragg angle between 10° to 70°. The microstructure grains growth of the BST powder was investigated by Scanning Electron Microscopy (SEM). Ba1-x(Sr)xTiO3 film was formed on naked p-Si (100) and oxide layer buffered p-Si (100) substrates by spin coating technique. After spin coating, subsequent annealing (500°C to 700°C) in oxygen and atmospheric ambient was followed to form the BST oxide film from BST sol solution coating. SEM investigation (planner and cross-sectional views) was carried out to examine the surface morphology and film thickness. Capacitance and voltage (C-V) characteristics of MFS and MFIS prototype devices were observed.<br>
2004
An overview is given on the use of ALD deposition technologies for high-k dielectrics and electrodes in MIM capacitors for embedded-DRAM in 90 nm technology and beyond. ALD-Al 2 O 3 and ALD-HfO 2 dielectrics have been evaluated together with MOCVD-Ta 2 O 5 for capacitors targeted at EOT < 18 A. Improved leakage performance was obtained through control of the dielectric/electrode interface. This includes the use of ALD-Al 2 O 3 as a thermo-dynamic and electronic barrier between Ta 2 O 5 and electrode and the use of ALD-TiN as electrode material. ALD-Al 2 O 3 and ALD-HfO 2 both give good leakage performance and stability with temperature, with HfO 2 offering most robust capacitance performance for next generation embedded-DRAM processes.
Journal of Applied Physics, 2002
This work is a systematic study of carbon incorporation in Ta2O5 and its effect on the material and electrical properties of Ta2O5, a promising replacement for silicon oxide in embedded dynamic random access memory applications. Using pulsed-dc reactive and rf-magnetron sputtering of Ta2O5 performed in an argon/oxygen/carbon-dioxide plasma, we have methodically doped the Ta2O5 films with carbon. In thick (70 nm) Ta2O5 films, an optimal amount (0.8–1.4 at. %) of carbon doping reduced the leakage current to 10−8 A/cm2 at +3 MV/cm, a four orders of magnitude reduction compared to a leakage current of 10−4 A/cm2 in an undoped Ta2O5 film grown in similar conditions without CO2 in the plasma. This finding suggests that carbon doping can further improve the dielectric leakage property at an optimal concentration. X-ray Photoemission Spectroscopy analysis showed the presence of carbonate (carbon bonded to three oxygen) in these electrically improved carbon-doped films. Analysis by high-reso...
Pt and RuO 2 Bottom Electrode Effects on Pb(Zr,Ti)O 3 Memory Capacitors
Japanese Journal of Applied Physics, 1999
This study examines the effects of bottom electrodes for metal ferroelectric metal (MFM) capacitor applications. We investigated the following parameters of bottom electrodes and Pb(Zr 0.53 Ti 0.47)O 3 (PZT) thin films: substrate temperature, rf power, gas flow rate, Ar/O 2 ratio, electrode material, and post-annealing effect. Bottom electrodes grown at 300 • C for Pt and 200 • C for RuO 2 exhibited a film resistivity of 10 −4 •cm, had a surface roughness of approximately 55 Å and a preferred crystal orientation. Rapid thermal annealing (RTA) treatments on a Pt electrode at 600 • C for 30 s improved the resistivity to 5 × 10 −6 •cm and generated the (111) preferred crystal orientation. PZT films exhibited a strong PZT (101) peak for an optimized Pt bottom electrode and (111), (200), (112) planes without preferred PZT orientations for the RuO 2 electrode. A well-fabricated Pd/PZT/Pt capacitor showed a leakage current density in the order of 6 × 10 −5 A/cm 2 , a dielectric constant (ε r) of 365, a remanent polarization (P r) of 27 µC/cm 2 , and a coercive field (E c) of 50.5 kV/cm. This paper discusses the bottom electrode properties as well as their recommended conditions in memory device applications of thin-film PZT capacitors.
Journal of Applied Physics, 2006
Due to the dependence on both bulk and interface properties neither the effective dielectric constant nor the leakage current J can be scaled in a straightforward manner with film thickness for highthin film capacitors. Based on detailed investigations of different thickness series of ͑Ba, Sr͒TiO 3 films on platinized substrates the bulk and interfacial properties are separated. An approach to estimate the apparent interfacial layer thickness is discussed. The behavior of the leakage current is divided in two regions: for low voltages, ഛ1 V, the currents are very low, ഛ10 −10 A/cm 2 , and dominated by the relaxation currents ͑Curie-von Schweidler behavior͒. At higher voltages the change to a very strong power law dependence is observed, J ϳ E 16. The thickness dependence is removed by scaling with the internal field or dielectric displacement of the film, D = 0 E. Hence, a direct connection between the increase in and the increase in leakage with film thickness is revealed. This behavior is accompanied by a larger scatter of the data and seems to be controlled by a more inhomogeneous or local conductivity. Influences of the measuring temperature and of stoichiometry and interfacial properties are discussed.
Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM
Solid-state Electronics, 2005
The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes.