A 15 BIT THIRD ORDER POWER OPTIMIZED CONTINUOUS TIME SIGMA DELTA MODULATOR FOR AUDIO APPLICATIONS (original) (raw)
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Sigma-Delta Modulator Design and Analysis for Audio Application
International Journal of Engineering Trends and Technology, 2015
A Sigma-delta modulator is designed in 180nm CMOS process for digital Audio applications. This design is simulated on S-Edit of Tanner EDA tool. In this design continuous time sigma-delta modulator is implemented to reduce the noise problem. This sigma-delta modulator also helps to reduce power consumption of circuit. In these design two stage op-amps is used to implement modulator. Also this design uses second order continuous time modulator for increasing SNR. Circuit design an 11bit low power sigma-delta modulator for digital audio application is given, using a single bit quantizer. The power supply for this circuit is only 1.8v; the modulator achieves 72dB SNR in a 20 KHz BW, while consuming 1mW.
Preliminary Design and Comparative Analysis Between Different DT Sigma-Delta Modulators
Sigma-Delta analog-to-digital converters (ADCs) are known for providing high resolutions when compared to other ADC architectures. They are composed of a sigma-delta modulator and a digital decimation filter. This work focuses is in the high-level design of discrete-time sigma-delta modulators (DT-SDMs) whereas the design and implementation of first and second-order modulators are analyzed using Matlab. A complete performance analysis of each modulator is described using the cascade of integrators in feedback (CIFB) structure. It is worth mentioning that our study has a focus on medium bandwidth (BW) applications, as such audio applications. Besides, we target low-voltage operations. This work is at an early stage, thus only first and second-order modulators are investigated. This work considers a BW of 24 kHz, a sampling frequency of 6.144 MHz, and oversampling (OSR) of 128. Index Terms-sigma-delta modulators, sigma-delta ADC, DT-SDM CIFB structure.
Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator
Ijacsa, 2012
This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.
A current-mode power sigma-delta modulator for audio applications
IEEE Transactions on Industrial Electronics, 2005
Linear and switching techniques are currently adopted to implement current-mode power stages. Pulsewidth modulation (PWM) is usually employed with the switching technique for both industrial and audio applications. In this paper, the Sigma-Delta modulation is considered as an alternative to the PWM in devising a switching current-mode power stage suitable for audio amplification. The proposed modulator is analyzed and simulated.
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .
Design of Low Power Discrete Time Sigma-Delta Modulator for Analog to Digital Converter
2014
Modulator is one of the most significant building-blocks in integrated discrete time component used in Sigma-Delta (ΣΔ) analog to digital converter. In this paper a novel structure of a switched-capacitor discrete time first order modulator Sigma-Delta is implemented at a supply voltage of 3 V. In addition, our design uses a Miller operational transconductance amplifier topology for low power consumption. The designed modulator has a resolution of 8 bits at a sampling frequency of 10.24 MHz. Eventually the modulator consumes only 1.16 mW of power under 3V. The core chip size of the modulator without bonding pads is 0.008 mm (76 μm x 110 μm) by using the AMS 0.35 μm CMOS technology.
International Journal of Research in Engineering and Technology, 2013
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .
A 3.3V Single-Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD
2000
This paper presents a second-order 16 modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-µm, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch-shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the-art performance in CMOS technology optimized for digital circuits.
2001
A 1-V 1-mW 14-bit 16 modulator in a standard CMOS 0.35- m technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz.
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .