CMOS scaling into the 21st century: 0.1 µm and beyond (original) (raw)

CMOS scaling into the 21st century: 0.1 µm and beyond

Ibm Journal of Research and Development, 1995

This paper describes the design, fabrication, and characterization of 0.1 -pm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2x performance gain over 2.54, 0.25-pm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20x reduction in active power per circuit is obtained at a supply voltage e1 V with the same delay as the 0.25-pm CMOS. These results demonstrate the feasibility of highperformance and low-power room-temperature 0.1-pm CMOS technology. Beyond 0.1 pm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed.

A high-performance 0.25- mu m CMOS technology. II. Technology

IEEE Transactions on Electron Devices, 1992

In this paper, the key technology elements and their integration into a high-performance, selectively scaled, 0.25-pm CMOS technology are presented. Dual poly gates (n' for nFET and p+ for pFET) are fabricated using a process, where the poly and source/drain (S/D) are doped simultaneously. The critical issues related to the dual poly gate, such as work Function and boron penetration through thin gate oxide (7 nm) are addressed. A reduced operating voltage of 2.5 V is used which allows the application of shallow junctions with abrupt profiles (no LDD) to minimize the device series resistance as well as gate to source/drain overlap capacitance. The poly gate and the S/D sheet resistances are lowered, using a thin salicide (TiSi2) process. The TiSi, thickness is reduced, as compared with the 0.5-pm CMOS process, to maintain the low leakage and low contact resistance for the shallow S / D junctions. To achieve low silicide sheet resistance, RTA processing is used, replacing the furnace anneals. The gate level with 0.4-pm physical length is defined using optical lithography with contrast enhanced layer (CEL) resist system. The CEL offers improved resolution and process control by producing vertical resist profiles down to the minimum dimensions. It also significantly reduces the interference effects and therefore the linewidth sensitivity to the resist thickness variations over topography *

A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications

2000

A modular 0.13 /spl mu/m CMOS platform has been developed to support a wide range of applications, including embedded non-volatile memory (NVM). The high performance core device with a 18 /spl Aring/ gate oxide supports the high end needs of the technology. In addition, medium performance and low leakage 25 /spl Aring/ devices are provided in the technology platform to service the low power applications, with low off-state leakage. The peripheral I/O devices support both 2.5 V (50 /spl Aring/) and 3.3 V (70 /spl Aring/) interfaces. Gate lengths range from 110 to 80 nm. Optical enhancement techniques allow use of 248 nm KrF lithography to meet the patterning needs. The interconnect technology allows for two low-k dielectric options with K-values in the range from 2.9 to 3.6. Aggressive design rules, fully compatible with 248 nm KrF systems allow for high logic densities and a 2.48 um/sup 2/ 6T embedded SRAM cell. The technology has been exercised using a 4MB SRAM test vehicle with good yields.

Supply and threshold voltage scaling for low power CMOS

IEEE Journal of Solid-state Circuits, 1997

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor. In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields.

CMOS scaling into the nanometer regime

Proceedings of The IEEE, 1997

Starting with a brief review on 0.1-m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations, and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may take us to the outermost limits of silicon scaling.

Device design, fabrication and characterization of 0.8 μm CMOS technology

1998

An intensive study has been conducted for the development of the MIMOS 0.8 μm CMOS technology. Issues such as device design and characterization have been given much consideration. NMOS and PMOS transistors have been designed from basic concepts and using simulation tools such as TSUPREM-4 and MEDICI. Device design constraints such as threshold voltage variation, off-state leakage current and drain-induced barrier lowering (DIBL) effects have been seriously examined to improve device performance. Furthermore, performance criteria such as drive current capability have also been examined. Extraction of device characteristics from silicon has been performed on a test chip. Based on experimental results, numerous I-V plots are presented and the data are discussed in terms of output and transfer characteristics and surface DIBL leakage current

Impact of technology scaling on the performance of domino CMOS logic

2008 International Conference on Electronic Design, 2008

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary CMOS logic family. To make the matter worse, these drawbacks are more tactile with the scaling of CMOS technology from one generation to the next. In this paper, the impact of CMOS technology scaling on the performance of domino CMOS logic will be investigated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in subthreshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with CMOS technology scaling due to the contention current of the keeper. A technique that extends the life time of domino logic in spite of CMOS technology scaling will be proposed. In fact, this technique aims to alleviate the effects of threshold-voltage reduction and the associated increase in subthreshold leakage on the noise immunity and the size of the PMOS keeper through the use of a current sensing circuit. This technique will be simulated for the 0.13 µm technology with power-supply voltage, V DD =1.2 V. Simulation results show that the proposed technique enhances the noise margin by approximately 560 mV and enhances the speed by approximately 56% compared to the conventional technique in which the gate of the PMOS keeper is connected to the output terminal, however, at the cost of an area penalty.

Scaling of Low Power CMOS Circuits with Optimum Performance

2014

In recent years, increasing demand for portable devices has made low power consumption a main design consideration. This paper optimizes the CMOS basic cells based on a simulation procedure to analyze how three aspects of IC power consumption, i.e. dynamic power, leakage power and peak power, can be considered together in optimizing the sizing and design of basic cells without a reduced degradation in performance with scaled supply voltage. The study was performed using basic cells in 32nm process technology for 1.8V to sub-1V by exploiting the linear dependency of supply voltage V DD and width of transistor W with circuit switching delay and power consumption. The optimization was carried out with 256-bit CMOS carry-ripple adder and 8-bit CMOS Braun multiplier as test vehicles. It is the aim of this paper to adopt a systematic approach to optimize CMOS basic cells with the use of RC delay modeling technique and geometry scaling to achieve optimum performance for low voltage adv...

Device scaling limits of Si MOSFETs and their application dependencies

Proceedings of The IEEE, 2001

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications. technology development group, Essex Junction, VT, to work on 1-Mb DRAM, and then began work on sub-half-micron MOSFETs for logic in 1984. He has contributed to numerous high-speed CMOS projects from 1.0-m to 0.1-m scales. He invented on 32 U.S. patents in the areas of CMOS circuits, devices and processes, and has authored numerous papers in these areas. He is currently engaged in the pursuit of sub-one-volt device designs and continues work on high-speed CMOS device design.