Determination of Thermal Induced Stresses in Semiconductor Chip Package by using Finite Element Analysis: A Brief Review (original) (raw)
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International Journal of Engineering Research and Technology (IJERT), 2015
https://www.ijert.org/determination-of-thermal-induced-stresses-in-semiconductor-chip-package-by-using-finite-element-analysis-a-brief-review https://www.ijert.org/research/determination-of-thermal-induced-stresses-in-semiconductor-chip-package-by-using-finite-element-analysis-a-brief-review-IJERTV4IS040112.pdf In todays advanced electrical technology, it becomes necessity to use compact semiconductor chips in variety of areas like computers, electrical appliances, automotive etc., clearly the need of more and more sophisticated packages is increasing. As the need of faster computer increases design of denser and more complicated packages becomes unavoidable, more complicated packages means that, the size of chip more or less remains same, but it has more electronic circuitry per unit surface area, this, of course increases the temperature of packages and causes thermal expansion due to change in coefficient of thermal expansion of the constituent materials. Thermal stresses ultimately cause the failure of the device. An IC package mainly consist of four parts, silicon die (chip), polymeric substrate, plastic molding compound and connectivity parts, lead frames and bond wires. The silicon chip is assembled on a polymeric substrate, plastic molding compound surrounding both parts, lead frames and bond wires provide electrical connectivity between the package and board on which assembly is made. The complicated geometrical structure and different material properties as well as the loading conditions made it almost impossible to study the mechanical behavior of semiconductor package analytically; therefore the finite element method has become a useful tool for evaluation of problems encountered in this area.
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010
On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete threedimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers.
An analytical model for thermal stress analysis of multi-layered microelectronic packaging
Compared to numerical methods, analytical solutions can offer a faster and more accurate procedure for obtaining the interfacial stresses in laminated structures. An analytical model for thermal stress analysis of multi-layered thin stacks on a thick substrate under isothermal loading is proposed in this paper. This analytical approach considers each layer as a beam-type plate with orthotropic material properties. Highly sensitive Moir e e interferometry is used to validate the model. The strain field in the bi-material interfaces is obtained experimentally. The test data is in good agreement with the proposed analytical solution. Finite element analysis results are also compared with the analytical solution and the test data.
Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The threedimensional numerical finite element model is capable to use geometric and material properties which are not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an X-ray diffraction method (Rocking-Curve-Technique) showin...
Thermomechanical Stress Analysis of Multi-Layered Electronic Packaging
An accurate estimate of thermal stresses in multilayered microelectronics structures along the bonded interfaces is crucial for design and prediction of delamination-related failures. Compared with a numerical method, analytical closed-form solution can offer a more rapid method to obtain the stresses at the interfaces. An analytical model for ply-level sub-laminate analysis is investigated in this paper. The theory presented treats each layer as a beam-type plate with orthotropic material properties. As an example , the results are shown for a three-layer beam problem with special orthotropic material properties. Analytical model results are compared with the finite element analysis results, as a first order approximation.
Microelectronics Reliability, 2008
The high residual stress in a resin-molded electronic package sometimes makes the electronic functions unstable. Therefore the residual stress in electronic packages, especially on the top surfaces of semiconductor chips, should be evaluated. The objective of this study is to present a simple method for evaluating residual stress in resin-molded semiconductor chips using a combination of experimental and numerical methods. The actual residual stress of the packaging process was measured by using test chips that included piezoresistive gauges. A linear thermoelastic finite element analysis was then carried out using a three-dimensional model. The finite element analysis was performed under a stress-free temperature determined by the temperature dependence of the residual stress, which was experimentally measured by using the piezoresistive test chips. The measured residual stress using the test chips agreed well with the results of the finite element analysis. It was therefore confirmed that the present evaluation method, combining experimental and numerical methods, is reliable and reasonable.
Analysis of Multilayered Microelectronic Packaging Under Thermal Gradient Loading
—An accurate estimation of interfacial and axial stresses in multilayered structures is important in the design process of microelectronic packaging because these stresses drive the failure modes in the package. During manufacturing, micro-electronic packaging devices usually suffer from severe thermal gradients. Design engineers often simplify the thermal gradient case as an isothermal loading case by averaging the temperature of the top and bottom of the microelectronic packaging device. Such simplification usually underestimates the stress level in the devices. With the analytical model presented in this paper, the stresses in multilayered microelectronic packaging devices subjected to thermal gradient loading can easily be predicted. It is shown that ignoring the thermal gradient in the package leads to underestimation of stresses.
International Symposium on Microelectronics, 2017
Distinct temperature and process dependent deformation behaviors under packaging temperature cycles are characterized for various packaging materials. Substrate and underfill deformations are described using Maxwell viscoelasticity model. Solder bump deformation is represented by incremental plasticity model. Anisotropic deformation in silicon and orthotropic deformation in substrate are also considered. The material deformation effects on stress evolutions during fabrication and under chip package interaction (CPI) are analyzed for a large package structure. Complex geometries spread over a large range of length scales are simulated using multi-level and multiscale sequential submodeling technique. Global package simulations show that substrate orthotropy has a significant impact on the package warpage during the assembly process. Sequential package assembly simulations are performed to examine the residual stresses at package, bump and interconnect scales. The results show that the package material behaviors during the assembly process affect not only the residual stresses in the large package structure but also in the local bump regions and the interconnect structures. The temperature dependent material non-linear behaviors under operating conditions also affect residual stresses and carrier mobility. This work demonstrates that developing performance and reliability management strategies under CPI should consider temperature and process dependent material deformations during fabrication and packaging.
Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping
ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1, 2011
Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/ speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete threedimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general "rule of thumb," approximately two-thirds ($66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to À 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.
Transient thermal analysis as measurement method for IC package structural integrity
Chinese Physics B, 2015
Practices of IC package reliability testing are reviewed briefly, and the application of transient thermal analysis is examined in great depth. For the design of light sources based on light emitting diode (LED) efficient and accurate reliability testing is required to realize the potential lifetimes of 10 5 h. Transient thermal analysis is a standard method to determine the transient thermal impedance of semiconductor devices, e.g. power electronics and LEDs. The temperature of the semiconductor junctions is assessed by time-resolved measurement of their forward voltage (V f). The thermal path in the IC package is resolved by the transient technique in the time domain. This enables analyzing the structural integrity of the semiconductor package. However, to evaluate thermal resistance, one must also measure the dissipated energy of the device (i.e., the thermal load) and the k-factor. This is time consuming, and measurement errors reduce the accuracy. To overcome these limitations, an innovative approach, the relative thermal resistance method, was developed to reduce the measurement effort, increase accuracy and enable automatic data evaluation. This new way of evaluating data simplifies the thermal transient analysis by eliminating measurement of the k-factor and thermal load, i.e. measurement of the lumen flux for LEDs, by normalizing the transient V f data. This is especially advantageous for reliability testing where changes in the thermal path, like cracks and delaminations, can be determined without measuring the k-factor and thermal load. Different failure modes can be separated in the time domain. The sensitivity of the method is demonstrated by its application to highpower white InGaN LEDs. For detailed analysis and identification of the failure mode of the LED packages, the transient signals are simulated by time-resolved finite element (FE) simulations. Using the new approach, the transient thermal analysis is enhanced to a powerful tool for reliability investigation of semiconductor packages in accelerated lifetime tests and for inline inspection. This enables automatic data analysis of the transient thermal data required for processing a large amount of data in production and reliability testing. Based on the method, the integrity of LED packages can be tested by inline, outgoing inspection and the lifetime prediction of the products is improved.